Hello Heiko and Sughosh,
On Wed, Feb 1, 2012 at 8:33 AM, Heiko Schocher hs@denx.de wrote:
Sughosh Ganu wrote:
On Tue, Jan 31, 2012 at 7:26 PM, Christian Riesch < christian.riesch@omicron.at> wrote:
The V bit of the c1 register of CP15 should not be cleared since the SoC has no valid memory at 0x00000000.
Signed-off-by: Christian Riesch christian.riesch@omicron.at Reported-by: Sughosh Ganu urwithsughosh@gmail.com Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com
arch/arm/cpu/arm926ejs/start.S | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index b39ed8a..b350480 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -372,7 +372,10 @@ flush_dcache: * disable MMU and D cache, and enable I cache */ mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS)
*/
- bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
+#ifndef CONFIG_SOC_DA850
- bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
+#endif
Instead of checking for a particular SOC, can we introduce a generic config, something like CONFIG_EXCEPTION_VECTORS_LOW. This way, if other SOC's have a similar requirement, it won't be needed to keep adding checks here. It would also help in case this needs to be implemented for other arm cores, so that we can have a common config option for bypassing this V-bit clear. Just my suggestion. Maybe Tom and Albert can comment.
Yep, I vote for this too, also this config option should be documented in the README.
Ok, I'll change this to
#ifdef CONFIG_EXCEPTION_VECTORS_HIGH orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ #else bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ #endif
Or should it be CONFIG_SYS_EXCEPTION_VECTORS_HIGH? I think I don't understand the explanation in README whether it should be _SYS_ or not.
Regards, Christian