From: Aaron Williams awilliams@marvell.com
Thips patch adds some more register definitions which will be used by the Octeon platform.
Signed-off-by: Aaron Williams awilliams@marvell.com Signed-off-by: Stefan Roese sr@denx.de ---
Changes in v2: None
arch/mips/include/asm/mipsregs.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 998f84d0a1..5214b3197e 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -40,15 +40,20 @@ #define CP0_CONF $3 #define CP0_GLOBALNUMBER $3, 1 #define CP0_CONTEXT $4 +#define CP0_USERLOCAL $4, 2 #define CP0_PAGEMASK $5 +#define CP0_PAGEGRAIN $5, 1 #define CP0_WIRED $6 #define CP0_INFO $7 #define CP0_HWRENA $7, 0 #define CP0_BADVADDR $8 #define CP0_BADINSTR $8, 1 #define CP0_COUNT $9 +#define CP0_CVMCOUNT $9, 6 +#define CP0_CVMCTL $9, 7 #define CP0_ENTRYHI $10 #define CP0_COMPARE $11 +#define CP0_CVMMEMCTL $11, 7 #define CP0_STATUS $12 #define CP0_CAUSE $13 #define CP0_EPC $14 @@ -56,8 +61,11 @@ #define CP0_EBASE $15, 1 #define CP0_CMGCRBASE $15, 3 #define CP0_CONFIG $16 +#define CP0_CONFIG1 $16, 1 #define CP0_CONFIG3 $16, 3 +#define CP0_CONFIG4 $16, 4 #define CP0_CONFIG5 $16, 5 +#define CP0_CVMMEMCTL2 $16, 6 #define CP0_LLADDR $17 #define CP0_WATCHLO $18 #define CP0_WATCHHI $19 @@ -67,13 +75,22 @@ #define CP0_DEBUG $23 #define CP0_DEPC $24 #define CP0_PERFORMANCE $25 +#define CP0_PERF_CNT0 $25, 1 +#define CP0_PERF_CNT1 $25, 3 +#define CP0_PERF_CNT2 $25, 5 +#define CP0_PERF_CNT3 $25, 7 #define CP0_ECC $26 #define CP0_CACHEERR $27 +#define CP0_CACHEERR_ICACHE $27 +#define CP0_CACHEERR_DCACHE $27, 1 #define CP0_TAGLO $28 #define CP0_TAGHI $29 #define CP0_ERROREPC $30 #define CP0_DESAVE $31 - +#define CP0_KSCRATCH1 $31, 2 +#define CP0_KSCRATCH2 $31, 3 +#define CP0_KSCRATCH3 $31, 4 +#define CP0_KSCRATCH4 $31, 5 /* * R4640/R4650 cp0 register names. These registers are listed * here only for completeness; without MMU these CPUs are not useable