Hello ,
We have a custom board similar to EP8548A board, custom board has MPC8548E alone with 4 onboard DDR2 SDRAM(total 512MB). Only one chip select is used. Below is the code snippet in u-boot, which will initialize the DDR2 SDRAM. Fortunately, When ever I give a hard reset( via switch) HRST# will be asserted and board will be Come up with the u-boot prompt.
But, when I give the command "reset" on the u-boot command line, system hangs printing The below on the console:
/*******************************************/ U-Boot 1.2.0 (Jan 27 2009 - 17:17:39)
CPU: 8548_E, Version: 2.1, (0x80390021) Core: E500, Version: 2.2, (0x80210022) Clock Configuration: CPU: 999 MHz, CCB: 399 MHz, DDR: 199 MHz, LBC: 49 MHz L1: D-cache 32 kB enabled I-cache 32 kB enabled Board: I2C: ready DRAM: Initializing DDR: 512 MB /*******************************************/
1) What might be the problem??? 2) I guess, after reinitializing the RAM this happened, but it is fine when I give a hard reset(using switch). 3) Is there any way that I should follow before re initializing the RAM.??? 4) As far as I know, in the below code snippet I'm doing the required stuffs.
Pls help me in this regard, at the earliest
/*************** ON Board, DDR2 SDRAM Initialization CODE Snippet********************? long int custom_sdram(void) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile ccsr_ddr_t *ddr = &immap->im_ddr; unsigned int memsize;
/*ddr sdram config: MEM_HALT & disable*/ ddr->sdram_cfg = 0x03000002; udelay(200);
/*Below are the calculated DDR2 controller register values*/ ddr->cs0_bnds = 0x0000001f; /* 0x2000 - DDR Chip Select 0 Memory Bounds */ ddr->cs1_bnds = 0x00000000; /* 0x2008 - DDR Chip Select 1 Memory Bounds */ ddr->cs2_bnds = 0x00000000; /* 0x2010 - DDR Chip Select 2 Memory Bounds */ ddr->cs3_bnds = 0x00000000; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
ddr->cs0_config = 0x80814102;/* 0x2080 - DDR Chip Select Configuration */ ddr->cs1_config = 0x00000000;/* 0x2084 - DDR Chip Select Configuration */ ddr->cs2_config = 0x00000000;/* 0x2088 - DDR Chip Select Configuration */ ddr->cs3_config = 0x00000000;/* 0x208c - DDR Chip Select Configuration */
ddr->ext_refrec = 0x00000000;/* 0x2100 - DDR SDRAM Extended Refresh Recovery */
ddr->timing_cfg_0 = 0xFF220802;/* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
ddr->timing_cfg_1 = 0x3835a322;/* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
ddr->timing_cfg_2 = 0x23108cca;/* 0x210c - DDR SDRAM Timing Configuration Register 2 */
ddr->sdram_mode = 0x40140432; /* 0x2118 - DDR SDRAM Mode Configuration */
ddr->sdram_interval = 0x06180100; /* 0x2124 - DDR SDRAM Interval Configuration */
asm("sync;isync;msync"); udelay(500);
ddr->sdram_cfg_2 = 0x04401000; /* 0x2114 - DDR SDRAM Control Configuration 2 */
ddr->sdram_clk_cntl = 0x02000000; /* 0x2130 - DDR SDRAM Clock Control */
udelay(200);
ddr->sdram_cfg = 0xc3008000;
asm("sync;isync;msync"); udelay(500);
/* * Figure out memory size in Megabytes. */ memsize = 512;
/* * Establish Local Access Window and TLB mappings for DDR memory. */ memsize = setup_laws_and_tlbs(memsize); if (memsize == 0) { return 0; } return memsize * 1024 * 1024; } /*******************************************/
Thanks, Ajeesh Kumar
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