Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/mpc8568mds/mpc8568mds.c | 137 ++++++++++--------------------- 1 files changed, 45 insertions(+), 92 deletions(-)
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index e2dc69e..60e22de 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor. + * Copyright 2007,2009 Freescale Semiconductor, Inc. * * (C) Copyright 2002 Scott McNutt smcnutt@artesyncp.com * @@ -311,8 +311,6 @@ static struct pci_controller pci1_hose = { static struct pci_controller pcie1_hose; #endif /* CONFIG_PCIE1 */
-int first_free_busno = 0; - /* * pib_init() -- Initialize the PCA9555 IO expander on the PIB board */ @@ -356,117 +354,72 @@ pib_init(void) }
#ifdef CONFIG_PCI -void -pci_init_board(void) +void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; - -#ifdef CONFIG_PCI1 -{ - pib_init(); - - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - struct pci_region *r = hose->regions; + struct fsl_pci_info pci_info[2]; + u32 devdisr, pordevsr, io_sel; + u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; + int first_free_busno = 0; + int num = 0;
- uint pci_32 = 1; /* PORDEVSR[15] */ - uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ - uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + int pcie_ep, pcie_configured;
- uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + porpllsr = in_be32(&gur->porpllsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint pci_speed = 66666000; + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
- if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { - printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", +#ifdef CONFIG_PCI1 + pci_speed = 66666000; + pci_32 = 1; + pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; + + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + SET_STD_PCI_INFO(pci_info[num], 1); + pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", - pci_arb ? "arbiter" : "external-arbiter" - ); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BUS, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BUS, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno = hose->last_busno+1; - printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); + pci_arb ? "arbiter" : "external-arbiter", + pci_info[num].regs); + + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); } else { - printf (" PCI: disabled\n"); + printf (" PCI: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif
#ifdef CONFIG_PCIE1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); - struct pci_region *r = hose->regions; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
- int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - - if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE connected to slot as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno); - - first_free_busno=hose->last_busno+1; + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { - printf (" PCIE: disabled\n"); + printf (" PCIE1: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif } #endif /* CONFIG_PCI */