Hi, the reason why the cache is not flushed, is that mips_cache_lock(stack pointer) (or so) is called before. This locks the whole data cache beginning from the stack pointer. Any other access to other addresses will not get into dcache, because the dcache lines are locked against replacing. See MIPS spec. Unfortunately the cache locking don't have to be implemented for MIPS 32 4Kc cpus. So the code i think has to be improved. I've implemented a fluch_cache routine to avoid the false behaviour, because the bcm47xx in my case doesn't support it (as it seems for me). On the other side icache don't has to be flushed before relocating, because the start code runs uncached from KSEG1. So my thoughts :) Anton
I too am going to implement a flush_cache routine to solve some issues. Are you going to feed back your fix for cpu/mips so flush_cache is available to all or when i get mine working should i feed mine back? cheers Dan
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