On Sunday 20 January 2008, Michael Schwingen wrote:
Mike Frysinger wrote:
I have not yet looked at the details of working with NAND flash, but the requirements should be similar. Maybe the NAND subsystem can be coerced to do what you need ...
i dont think nand would be as much of a problem as it isnt directly addressable. you have to go through the "nand" subsystem for reading/writing while with parallel nor flash, it's directly addressable.
Well, your parallel flash is *not* directly addressable
only some chunks are directly addressable at any one time. but you're right that if you look at the whole thing, it isnt.
another (probably saner) option is to implement a new subsystem, say "flash" or "gnor" (GPIO NOR). it'd have the same basic semantics/syntax as the nand or eeprom commands where you cannot access the flash directly, but instead read/write chunks to/from external memory. to keep code duplication down, it'd hook into the common cfi driver for the lower layer functions ... -mike