Hi Stefan,
I don't have much knowledge about how u-boot being implemented.
Why is this? Which "Board Memory Map" are you referring to?
I am referring to 'Peripheral Registers' table given in 'PPC440GX® Evaluation Board User’s Manual'. I found the 32 bit value passed to the 'telbentry' macro is matching with the values given in the '32 Bit Address' column of the table except for 'PCI Memory - cached'. And this mismatch confused me.
From your last reply I understood that it is the developer who got the freedom to decide the 32-bit value. Is that correct?
Regards, Sachin
Stefan Roese wrote:
On Monday 16 June 2008, Sachin Rane wrote:
Infact I was looking for the info to create a proper 'tlbentry' in 'init.S' As per my understanding the 'tlbentry' is to map 32-bit address to 36-bit address.
The 'tlbenry' for the PCI Memory in 'init.S' is : tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
The 'CFG_PCI_MEMBASE' is set to 0x80000000 in 'ocotea.h'.
My question is how to select the value for 'CFG_PCI_MEMBASE'. Can I use any value (say 0x50000000 ) provided it is not overlapping with other devices?
Yes. I suggest to start with 0x80000000 since this leaves the first 2 GB for SDRAM.
If we are using Board Memory Map as a reference then the 32-bit address 'CFG_PCI_MEMBASE' used in 'telbentry' should have set to: 0x90000000
Why is this? Which "Board Memory Map" are you referring to?
I am trying to find out the logic behind the selection of value for the variabale 'CFG_PCI_MEMBASE' in: tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
Whats the problems with using 0x80000000 here?
Best regards, Stefan
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