From: Ying Zhang b40530@freescale.com
Support TPL on the P1022DS. The TPL's size is sizeable, the maximum size must not exceed the size of L2 SRAM. It initializes the DDR through SPD code, and copys final uboot image to DDR. So there are three stage uboot images: * spl_boot, 4KB size, pad to 128K byte. * tpl_boot, 88K size, pad to 128K size. The env variables are copied to L2 SRAM, so that ddr SPD code can get the interleaving mode setting in env. It loads final uboot image from offset 256KB. * final uboot image, size is variable depends on the functions enabled.
This patch is on top of the patch: nand: tpl : introduce the TPL based on the SPL
Signed-off-by: Ying Zhang b40530@freescale.com --- Compared with the original version, Changed as below: 1. Split from "powerpc/p1022ds: nand: introduce the TPL based on the SPL". 2. No change. 3. No change. 4. No change. 5. Change functionality nand_load_image to nand_load, it is called in TPL.
Makefile | 3 +- arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 4 + board/freescale/p1022ds/Makefile | 3 + board/freescale/p1022ds/spl_minimal.c | 57 ++--------------- board/freescale/p1022ds/tlb.c | 4 +- board/freescale/p1022ds/tpl.c | 102 +++++++++++++++++++++++++++++++ drivers/mtd/nand/fsl_elbc_spl.c | 8 +- include/configs/P1022DS.h | 77 ++++++++++++++++++----- 8 files changed, 184 insertions(+), 74 deletions(-) create mode 100644 board/freescale/p1022ds/tpl.c
diff --git a/Makefile b/Makefile index 0513e4d..a3c7282 100644 --- a/Makefile +++ b/Makefile @@ -895,7 +895,7 @@ clobber: tidy @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map} @rm -f $(obj)spl/u-boot-spl.lds @rm -f $(obj)tpl/{u-boot-tpl,u-boot-tpl.bin,u-boot-tpl.map} - @rm -f $(obj)tpl/u-boot-tpl.lds + @rm -f $(obj)tpl/u-boot-spl.lds @rm -f $(obj)MLO MLO.byteswap @rm -f $(obj)SPL @rm -f $(obj)tools/xway-swap-bytes @@ -906,6 +906,7 @@ clobber: tidy @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f @rm -f $(obj)dts/*.tmp @rm -f $(obj)spl/u-boot-spl{,-pad}.ais + @rm -f $(obj)tpl/u-boot-tpl{,-pad}.ais
mrproper \ distclean: clobber unconfig diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 8aeb1a0..3167d2d 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -35,7 +35,11 @@ PHDRS #endif SECTIONS { +#ifdef CONFIG_SPL_BUILD . = CONFIG_SPL_TEXT_BASE; +#else + . = CONFIG_TPL_TEXT_BASE; +#endif .text : { *(.text*) } diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile index 9746063..58f224e 100644 --- a/board/freescale/p1022ds/Makefile +++ b/board/freescale/p1022ds/Makefile @@ -27,6 +27,9 @@ else ifdef CONFIG_SPL_BUILD COBJS-y += spl.o endif +ifdef CONFIG_TPL_BUILD +COBJS-y += tpl.o +endif COBJS-y += $(BOARD).o COBJS-y += ddr.o COBJS-y += law.o diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c index 8d12fa6..8ab5ec2 100644 --- a/board/freescale/p1022ds/spl_minimal.c +++ b/board/freescale/p1022ds/spl_minimal.c @@ -27,51 +27,6 @@ #include <asm/fsl_ddr_sdram.h>
-/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -void sdram_init(void) -{ - volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - - __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); - __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); -#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 - __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); - __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); -#endif - __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); - - __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); - - __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); - - __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); - __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); - __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl); - - /* Set, but do not enable the memory */ - __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, - &ddr->sdram_cfg); - - in_be32(&ddr->sdram_cfg); - udelay(500); - - /* Let the controller go */ - out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); - in_be32(&ddr->sdram_cfg); - - set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1); -} - const static u32 sysclk_tbl[] = { 66666000, 7499900, 83332500, 8999900, 99999000, 11111000, 12499800, 13333200 @@ -83,6 +38,10 @@ void board_init_f(ulong bootflag) u32 plat_ratio, sys_clk, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); +#endif /* for FPGA */ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); @@ -98,19 +57,17 @@ void board_init_f(ulong bootflag)
puts("\nNAND boot... ");
- /* Initialize the DDR3 */ - sdram_init(); - /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, - CONFIG_SPL_RELOC_TEXT_BASE); + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, + CONFIG_SYS_NAND_U_BOOT_RELOC); }
void board_init_r(gd_t *gd, ulong dest_addr) { + puts("\nSecond program loader running in sram..."); nand_boot(); }
diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c index 9b14c37..aed8b86 100644 --- a/board/freescale/p1022ds/tlb.c +++ b/board/freescale/p1022ds/tlb.c @@ -41,7 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1),
-#ifndef CONFIG_SPL_BUILD +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) /* W**G* - Flash/promjet, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, @@ -75,7 +75,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 7, BOOKE_PAGESZ_4K, 1),
#if defined(CONFIG_SYS_RAMBOOT) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) + (defined(CONFIG_SPL) && !defined(CONFIG_COMMON_INIT_DDR)) /* **** - eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, diff --git a/board/freescale/p1022ds/tpl.c b/board/freescale/p1022ds/tpl.c new file mode 100644 index 0000000..628b9e8 --- /dev/null +++ b/board/freescale/p1022ds/tpl.c @@ -0,0 +1,102 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ns16550.h> +#include <malloc.h> +#include <i2c.h> +#include <nand.h> +#include "../common/ngpixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +static const u32 sysclk_tbl[] = { + 66666000, 7499900, 83332500, 8999900, + 99999000, 11111000, 12499800, 13333200 +}; + +ulong get_effective_memsize(void) +{ + return CONFIG_SYS_L2_SIZE; +} + +void board_init_f(ulong bootflag) +{ + int px_spd; + u32 plat_ratio, sys_clk, bus_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + console_init_f(); + /* Set pmuxcr to allow both i2c1 and i2c2 */ + setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); + setbits_be32(&gur->pmuxcr, + in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); + + /* Read back the register to synchronize the write. */ + in_be32(&gur->pmuxcr); + + /* initialize selected port with appropriate baud rate */ + px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD)); + sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK]; + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + bus_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *)CONFIG_SYS_GD_ADDR; + bd_t *bd; + + memset(gd, 0, sizeof(gd_t)); + bd = (bd_t *)(CONFIG_SYS_GD_ADDR + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; + bd->bi_memsize = CONFIG_SYS_L2_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SYS_RELOC_MALLOC_ADDR, \ + CONFIG_SYS_RELOC_MALLOC_SIZE); + /* relocate environment function pointers etc. */ + nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + gd->ram_size = initdram(0); + puts("Tertiary program loader running in sram..."); + + nand_boot(); +} diff --git a/drivers/mtd/nand/fsl_elbc_spl.c b/drivers/mtd/nand/fsl_elbc_spl.c index ab208fd..8924e2d 100644 --- a/drivers/mtd/nand/fsl_elbc_spl.c +++ b/drivers/mtd/nand/fsl_elbc_spl.c @@ -50,7 +50,7 @@ static void nand_wait(void) #ifdef CONFIG_SPL_BUILD static #endif -int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) +int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst) { fsl_lbc_t *regs = LBC_BASE_ADDR; uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; @@ -140,16 +140,16 @@ void nand_boot(void) /* * Load U-Boot image from NAND into RAM */ - nand_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, (void *)CONFIG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST - nand_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, (void *)CONFIG_NAND_ENV_DST);
#ifdef CONFIG_ENV_OFFSET_REDUND - nand_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, + nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); #endif #endif diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 9e012c4..42e4f42 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -44,7 +44,7 @@ #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #define CONFIG_SPL_MMC_BOOT #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_COMMON_INIT_DDR #endif #endif
@@ -75,7 +75,7 @@ #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #define CONFIG_SPL_SPI_BOOT #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_COMMON_INIT_DDR #endif #endif
@@ -83,22 +83,41 @@
#ifdef CONFIG_NAND #define CONFIG_SPL +#define CONFIG_TPL #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SYS_TEXT_BASE 0x00201000 -#define CONFIG_SPL_TEXT_BASE 0xfffff000 -#define CONFIG_SPL_MAX_SIZE 4096 -#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 -#define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 -#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_TEXT_BASE 0xff800000 +#define CONFIG_SPL_MAX_SIZE 4096 +#define CONFIG_SPL_PAD_TO 0x20000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) +#endif +#define CONFIG_SYS_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SYS_ENV_SUPPORT +#define CONFIG_SYS_SERIAL_SUPPORT +#define CONFIG_SYS_LIBGENERIC_SUPPORT +#define CONFIG_SYS_LIBCOMMON_SUPPORT +#define CONFIG_SYS_I2C_SUPPORT +#define CONFIG_SYS_NAND_SUPPORT +#define CONFIG_TPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SYS_MAX_SIZE (128 << 10) +#define CONFIG_SYS_PAD_TO 0x20000 +#ifdef CONFIG_TPL_BUILD +#define CONFIG_COMMON_INIT_DDR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) +#endif +#define CONFIG_SPL_TARGET "u-boot-with-tpl.bin" +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #endif
/* High Level Configuration Options */ @@ -153,7 +172,7 @@
/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k SPL code*/ -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_TPL_BUILD) #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif
@@ -254,6 +273,8 @@ #ifndef CONFIG_SYS_MONITOR_BASE #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#elif defined(CONFIG_TPL_BUILD) +#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE #else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif @@ -335,7 +356,7 @@ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (576 * 1024) #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
/* @@ -353,7 +374,24 @@ #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) #endif +#elif defined(CONFIG_TPL_BUILD) +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0xf8f81000 +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) +#define CONFIG_SYS_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) +#define CONFIG_SYS_RELOC_MALLOC_SIZE (48 << 10) +#define CONFIG_SYS_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) #endif
@@ -603,8 +641,13 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 #elif defined(CONFIG_NAND) #define CONFIG_ENV_IS_IN_NAND +#ifdef CONFIG_TPL_BUILD +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#else #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#endif +#define CONFIG_ENV_OFFSET (1024 * 1024) #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) #elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */