The RCW print is common for all corenet platforms. Not necessary to ducplicate in each board file.
Signed-off-by: York Sun yorksun@freescale.com --- arch/powerpc/cpu/mpc85xx/cpu.c | 23 +++++++++++++++++++---- board/freescale/b4860qds/b4860qds.c | 15 --------------- board/freescale/corenet_ds/corenet_ds.c | 17 +++-------------- board/freescale/p2041rdb/p2041rdb.c | 15 --------------- board/freescale/t4qds/t4qds.c | 14 -------------- 5 files changed, 22 insertions(+), 62 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 6ce483e..d407373 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -60,10 +60,10 @@ int checkcpu (void) uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; -#if (defined(CONFIG_DDR_CLK_FREQ) || \ - defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#endif /* CONFIG_FSL_CORENET */ +#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) + ccsr_gur_t __iomem *gur = + (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif
/* * Cornet platforms use ddr sync bit in RCW to indicate sync vs async @@ -227,6 +227,21 @@ int checkcpu (void)
puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
+#ifdef CONFIG_FSL_CORENET + /* Display the RCW, so that no one gets confused as to what RCW + * we're actually using for this boot. + */ + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + u32 rcw = in_be32(&gur->rcwsr[i]); + + if ((i % 4) == 0) + printf("\n %08x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); +#endif + return 0; }
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index a39c17a..8058c78 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -51,8 +51,6 @@ int checkboard(void) char buf[64]; u8 sw; struct cpu_type *cpu = gd->arch.cpu; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - unsigned int i; static const char *const freq[] = {"100", "125", "156.25", "161.13", "122.88", "122.88", "122.88"}; int clock; @@ -77,19 +75,6 @@ int checkboard(void) /* the timestamp string contains "\n" at the end */ printf(" on %s", qixis_read_time(buf));
- /* Display the RCW, so that no one gets confused as to what RCW - * we're actually using for this boot. - */ - puts("Reset Configuration Word (RCW):"); - for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_be32(&gur->rcwsr[i]); - - if ((i % 4) == 0) - printf("\n %08x:", i * 4); - printf(" %08x", rcw); - } - puts("\n"); - /* * Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 48f7155..22677a9 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -43,8 +43,10 @@ int checkboard (void) { u8 sw; struct cpu_type *cpu = gd->arch.cpu; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) || \ + defined(CONFIG_P5040DS) unsigned int i; +#endif static const char * const freq[] = {"100", "125", "156.25", "212.5" };
printf("Board: %sDS, ", cpu->name); @@ -63,19 +65,6 @@ int checkboard (void) else printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
- /* Display the RCW, so that no one gets confused as to what RCW - * we're actually using for this boot. - */ - puts("Reset Configuration Word (RCW):"); - for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_be32(&gur->rcwsr[i]); - - if ((i % 4) == 0) - printf("\n %08x:", i * 4); - printf(" %08x", rcw); - } - puts("\n"); - /* Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could * technically be set to force the reference clocks to match the diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 44d3e0c..cc4c6af 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -44,7 +44,6 @@ int checkboard(void) { u8 sw; struct cpu_type *cpu = gd->arch.cpu; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; unsigned int i;
printf("Board: %sRDB, ", cpu->name); @@ -55,20 +54,6 @@ int checkboard(void) printf("vBank: %d\n", sw & 0x1);
/* - * Display the RCW, so that no one gets confused as to what RCW - * we're actually using for this boot. - */ - puts("Reset Configuration Word (RCW):"); - for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_be32(&gur->rcwsr[i]); - - if ((i % 4) == 0) - printf("\n %08x:", i * 4); - printf(" %08x", rcw); - } - puts("\n"); - - /* * Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could * technically be set to force the reference clocks to match the diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c index f0f280b..67de0ea 100644 --- a/board/freescale/t4qds/t4qds.c +++ b/board/freescale/t4qds/t4qds.c @@ -59,7 +59,6 @@ int checkboard(void) char buf[64]; u8 sw; struct cpu_type *cpu = gd->arch.cpu; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; unsigned int i;
printf("Board: %sQDS, ", cpu->name); @@ -84,19 +83,6 @@ int checkboard(void) /* the timestamp string contains "\n" at the end */ printf(" on %s", qixis_read_time(buf));
- /* Display the RCW, so that no one gets confused as to what RCW - * we're actually using for this boot. - */ - puts("Reset Configuration Word (RCW):"); - for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_be32(&gur->rcwsr[i]); - - if ((i % 4) == 0) - printf("\n %08x:", i * 4); - printf(" %08x", rcw); - } - puts("\n"); - /* * Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could