On 2/13/19 3:18 PM, tien.fong.chee@intel.com wrote:
From: Tien Fong Chee tien.fong.chee@intel.com
Add default fitImage file bundling FPGA bitstreams for Arria10.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
changes for v8
- Changed the FPGA node name to fpga-core and fpga-periph for both core and periph bitstreams respectively.
board/altera/arria10-socdk/fit_spl_fpga.its | 39 +++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its
diff --git a/board/altera/arria10-socdk/fit_spl_fpga.its b/board/altera/arria10-socdk/fit_spl_fpga.its new file mode 100644 index 0000000..8ce175b --- /dev/null +++ b/board/altera/arria10-socdk/fit_spl_fpga.its @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0
- /*
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+/dts-v1/;
+/ {
- description = "FIT image with FPGA bistream";
- #address-cells = <1>;
- images {
fpga-core@1 {description = "FPGA core bitstream";data = /incbin/("../../../ghrd_10as066n2.core.rbf");type = "fpga";arch = "arm";compression = "none";load = <0x400>;
Is the load address required ?
};fpga-periph@2 {description = "FPGA peripheral bitstream";data = /incbin/("../../../ghrd_10as066n2.periph.rbf");type = "fpga";arch = "arm";compression = "none";};- };
- configurations {
default = "config-1";config-1 {description = "Boot with FPGA early IO release config";fpga = "fpga-periph@2", "fpga-core@1";
Don't you need to load the core first ?
};- };
+};