From: Hao Zhang hzhang@ti.com
Add DDR3 PHY configs updated for PG 2.0 Also add DDR3A PHY reset before init for PG2.0 SoCs.
Acked-by: Murali Karicheri m-maricheri2@ti.com Signed-off-by: Hao Zhang hzhang@ti.com Signed-off-by: Ivan Khoronzhuk ivan.khoronzhuk@ti.com --- arch/arm/cpu/armv7/keystone/ddr3.c | 19 +++++++ arch/arm/include/asm/arch-keystone/ddr3.h | 1 + arch/arm/include/asm/arch-keystone/hardware.h | 2 + board/ti/k2hk_evm/ddr3.c | 80 ++++++++++++++++++++++++++- 4 files changed, 100 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c index bb16551..b711b81 100644 --- a/arch/arm/cpu/armv7/keystone/ddr3.c +++ b/arch/arm/cpu/armv7/keystone/ddr3.c @@ -8,6 +8,7 @@ */
#include <asm/io.h> +#include <common.h> #include <asm/arch/ddr3.h>
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) @@ -67,3 +68,21 @@ void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET); __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET); } + +void ddr3_reset_ddrphy(void) +{ + u32 tmp; + + /* Assert DDR3A PHY reset */ + tmp = readl(K2HK_DDR3APLLCTL1); + tmp |= KS2_DDR3_PLLCTRL_PHY_RESET; + writel(tmp, K2HK_DDR3APLLCTL1); + + /* wait 10us to catch the reset */ + udelay(10); + + /* Release DDR3A PHY reset */ + tmp = readl(K2HK_DDR3APLLCTL1); + tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET; + __raw_writel(tmp, K2HK_DDR3APLLCTL1); +} diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h index 05b7e29..4d229a2 100644 --- a/arch/arm/include/asm/arch-keystone/ddr3.h +++ b/arch/arm/include/asm/arch-keystone/ddr3.h @@ -49,6 +49,7 @@ struct ddr3_emif_config { };
void ddr3_init(void); +void ddr3_reset_ddrphy(void); void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index f8f986c..db2d36b 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -80,6 +80,8 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_DDR3_PMCTL_OFFSET 0x38 #define KS2_DDR3_ZQCFG_OFFSET 0xC8
+#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000 + #define KS2_UART0_BASE 0x02530c00 #define KS2_UART1_BASE 0x02531000
diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c index 0085f29..b604266 100644 --- a/board/ti/k2hk_evm/ddr3.c +++ b/board/ti/k2hk_evm/ddr3.c @@ -188,6 +188,61 @@ static struct ddr3_phy_config ddr3phy_1333_64 = { .pir_v2 = 0x0000FF81ul, }; /******************************************************/ + +/* DDR PHY Configs Updated for PG 2.0 + * zq0,1,2cr1 are updated for PG 2.0 specific configs *_pg2 */ +static struct ddr3_phy_config ddr3phy_1600_64A_pg2 = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0D861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0xA19DBB66ul, + .dtpr1 = 0x32868300ul, + .dtpr2 = 0x50035200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x730035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +static struct ddr3_phy_config ddr3phy_1333_64A_pg2 = { + .pllcr = 0x0005C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0B4515C2ul, + .ptr4 = 0x0A6E08B4ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x8558AA55ul, + .dtpr1 = 0x32857280ul, + .dtpr2 = 0x5002C200ul, + .mr0 = 0x00001A60ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000010ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F065B8ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + int get_dimm_params(char *dimm_name) { u8 spd_params[256]; @@ -240,7 +295,18 @@ void ddr3_init(void) if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { init_pll(&ddr3a_400); if (cpu_revision() > 0) { - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A); + if (cpu_revision() > 1) { + /* PG 2.0 */ + /* Reset DDR3A PHY after PLL enabled */ + ddr3_reset_ddrphy(); + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + &ddr3phy_1600_64A_pg2); + } else { + /* PG 1.1 */ + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + &ddr3phy_1600_64A); + } + ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64); printf("DRAM: Capacity 8 GiB (includes reported below)\n"); @@ -253,7 +319,17 @@ void ddr3_init(void) } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { init_pll(&ddr3a_333); if (cpu_revision() > 0) { - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A); + if (cpu_revision() > 1) { + /* PG 2.0 */ + /* Reset DDR3A PHY after PLL enabled */ + ddr3_reset_ddrphy(); + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + &ddr3phy_1333_64A_pg2); + } else { + /* PG 1.1 */ + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + &ddr3phy_1333_64A); + } ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64); } else {