On Mon, 19 Apr 2010 15:19:24 -0500 Scott Wood scottwood@freescale.com wrote:
Kim Phillips wrote:
On Fri, 16 Apr 2010 20:06:02 +0300 Michael Zaidman michael.zaidman@gmail.com wrote:
On Fri, Apr 16, 2010 at 1:36 AM, Kim Phillips kim.phillips@freescale.com wrote:
before, MPC8349ITX boots u-boot in 4.3sec:
[snip]
after, MPC8349ITX boots u-boot in 3.0sec:
Thanks for the good news! Memory POST test on my board with icach disabled was lasting for hours until I enabled icach locally before and disabled it after time consuming tests.
BTW is there any reason that you enable icach in board specific rather than in common code?
not really, was just following the existing HID0-setting paradigm - I presume the paradigm came about to allow different cpu/board combinations to enable/disable different HID bits. Does that not sound valid to you?
Shouldn't you be using icache_enable(), or at least using HID0_INIT to do invalidation and lock clearing?
the invalidation should occur whether or not the cache enable bit is set in HID0_INIT, and there is no locking being done prior to this point in the code. But I see your point; we should be using a more formal approach. I'll see what I can do - it's just that this patch preserved the existing code size, which could be important for e.g., future nand bootstrap development.
Kim