On Fri, Jan 27, 2012 at 10:09 AM, Robert Nelson robertcnelson@gmail.com wrote:
On Fri, Jan 27, 2012 at 10:51 AM, Robert Nelson robertcnelson@gmail.com wrote:
On Fri, Jan 27, 2012 at 10:25 AM, Tom Rini tom.rini@gmail.com wrote:
On Fri, Jan 27, 2012 at 9:23 AM, Robert Nelson robertcnelson@gmail.com wrote:
On Fri, Jan 27, 2012 at 9:58 AM, Tom Rini tom.rini@gmail.com wrote:
On Fri, Jan 27, 2012 at 8:50 AM, wilsonjonathan piercing_male@hotmail.com wrote:
I think the area of code that needs investigating is in arch/arm/cpu/armv7/omap3/sdrc.c
line 82 onwards :-
> u32 get_sdr_cs_size(u32 cs) > { > u32 size; > > /* get ram size field */ > size = readl(&sdrc_base->cs[cs].mcfg) >> 8; > size &= 0x3FF; /* remove unwanted bits */ > size <<= 21; /* multiply by 2 MiB to find size in MB */ > return size; > } >
Which I think is set in arc/arm/include/asm/arch-omap3/cpu.h but I don't understand how the -> stuff works.
This is all correct. However, what's going wrong is we're programming the size of memory found incorrectly and we don't yet have a safe method to probe how much memory is really there (aside: get_ram_size(...) goes off into the weeds on omap3 and it's on my TODO list, and rising fast, to get my flyswatter out, hooked up and see what's really happening). So what I really need to know is which of the cases in beagle.c this board is falling into (I suspect it's the top half of that else, but it's 2x128MB not 1x256). Thanks again!
Okay, little bit more information is shown with printf's..
U-Boot SPL 2011.12-00001-g35bbe6c-dirty (Jan 27 2012 - 10:15:33) Texas Instruments Revision detection unimplemented case REVISION_C4: actual pop_id: 0xBA actual pop_mfr: 0x2C case REVISION_C4: Neither option was selected. OMAP SD/MMC: 0 reading u-boot.img reading u-boot.img
using:
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 9aa05d4..4c7bf94 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -158,7 +158,11 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, *mr = MICRON_V_MR_165; switch (get_board_revision()) { case REVISION_C4:
- printf("case REVISION_C4:\n");
- printf("actual pop_id: 0x%02X \n", pop_id);
- printf("actual pop_mfr: 0x%02X \n", pop_mfr);
if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
- printf("pop_id == 0xba (C4)\n");
/* Beagleboard Rev C4, 256MB DDR */ *mcfg = NUMONYX_V_MCFG_165(256 << 20); *ctrla = NUMONYX_V_ACTIMA_165; @@ -166,6 +170,7 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
- printf("pop_id == 0xbc (c5)\n");
/* Beagleboard Rev C5, 256MB DDR */ *mcfg = MICRON_V_MCFG_200(256 << 20); *ctrla = MICRON_V_ACTIMA_200; @@ -173,6 +178,7 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; }
- printf("case REVISION_C4: Neither option was selected.\n");
case REVISION_XM_A: case REVISION_XM_B: case REVISION_XM_C:
On my c4, it looks like neither option is selected for it..
./include/linux/mtd/nand.h:#define NAND_MFR_STMICRO 0x20 ./include/linux/mtd/nand.h:#define NAND_MFR_MICRON 0x2c
looks like the RAM/NAND options might have been reversed for C4 and C5 in the IF statement.. but i dont' have a C5 to test..
I've got a C5 which has been OK. I've got to step out for a few but I'll have a patch later today for this I hope, if you don't beat me to it :)
Ah, now i see the problem.. There actually isn't support in u-boot for the regular C4.. ;)
When the memory options where transfered from x-loader. The special 'white label' 512Mb DDR C4 from Special Computing became the "regular C4"..
see: http://gitorious.org/x-loader/x-loader/blobs/master/board/omap3530beagle/oma...
and
http://gitorious.org/x-loader/x-loader/commit/1dac1a7c188e79edabe211ccaadf58...
So first we need to document the "512MB DDR" something like...
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 6a457cb..cf55c79 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -159,7 +159,7 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, switch (get_board_revision()) { case REVISION_C4: if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
- /* 512MB DDR */
- /* Beagle Rev C4 from Special Computing, 512MB DDR */
*mcfg = NUMONYX_V_MCFG_165(512 << 20); *ctrla = NUMONYX_V_ACTIMA_165; *ctrlb = NUMONYX_V_ACTIMB_165;
and then readd c4 memory timings..
Okay with:
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index cf55c79..226d7dc 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -165,6 +165,13 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, *ctrlb = NUMONYX_V_ACTIMB_165; *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break;
- } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
- /* Beagleboard Rev C4, 512MB Nand/256MB DDR*/
- *mcfg = MICRON_V_MCFG_165(128 << 20);
- *ctrla = MICRON_V_ACTIMA_165;
- *ctrlb = MICRON_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- break;
} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) { /* Beagleboard Rev C5, 256MB DDR */ *mcfg = MICRON_V_MCFG_200(256 << 20);
OMAP3530-GP ES3.1, CPU-OPP2, L3-165MHz, Max CPU Clock 720 mHz OMAP3 Beagle board + LPDDR/NAND I2C: ready DRAM: 256 MiB NAND: 256 MiB MMC: OMAP SD/MMC: 0
The DRAM is now correct... but now to fix the NAND, it should be 512MiB.. ;)
Good catch! Can you reply with a Signed-off-by line and I'll incorporate this into u-boot-ti/master? Thanks!