This patchset is intended to enable L2-cache in U-boot SPL, along with cache operations cleanup for AE350 platforms.
Leo Yu-Chi Liang (1): riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"
Yu Chien Peter Lin (10): riscv: global_data.h: Correct the comment for PLICSW board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init() driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init() riscv: ae350: dts: Update L2 cache compatible string riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL configs: ae350: Enable v5l2 cache for AE350 platforms configs: ae350: Increase maximum retry count for AE350 platforms configs: ae350: Display CPU and board info for AE350 platforms driver: cache-v5l2: Fix type casting warning on RV32
arch/riscv/cpu/ax25/Kconfig | 10 -- arch/riscv/cpu/ax25/cache.c | 120 ++++++++---------------- arch/riscv/cpu/ax25/cpu.c | 46 +++------ arch/riscv/dts/ae350_32.dts | 2 +- arch/riscv/dts/ae350_64.dts | 2 +- arch/riscv/include/asm/arch-andes/csr.h | 29 ++++++ arch/riscv/include/asm/global_data.h | 2 +- board/AndesTech/ax25-ae350/ax25-ae350.c | 17 ++-- configs/ae350_rv32_defconfig | 4 + configs/ae350_rv32_spl_defconfig | 6 ++ configs/ae350_rv32_spl_xip_defconfig | 6 ++ configs/ae350_rv32_xip_defconfig | 4 + configs/ae350_rv64_defconfig | 4 + configs/ae350_rv64_spl_defconfig | 6 ++ configs/ae350_rv64_spl_xip_defconfig | 6 ++ configs/ae350_rv64_xip_defconfig | 4 + drivers/cache/Kconfig | 1 - drivers/cache/cache-v5l2.c | 36 +++++-- 18 files changed, 158 insertions(+), 147 deletions(-) create mode 100644 arch/riscv/include/asm/arch-andes/csr.h