SPI controllers SSP1, 2 and 3 require to enable their respective clocks. Let's enable them only when the SPI controller driver is built.
Signed-off-by: Quentin Schulz quentin.schulz@bootlin.com ---
v2: - define and use constants for enabling SSP1/2/3 clocks when the controller is built
arch/arm/cpu/arm926ejs/spear/cpu.c | 3 +++ arch/arm/include/asm/arch-spear/spr_misc.h | 2 ++ 2 files changed, 5 insertions(+)
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c index 6fc29e7..c572785 100644 --- a/arch/arm/cpu/arm926ejs/spear/cpu.c +++ b/arch/arm/cpu/arm926ejs/spear/cpu.c @@ -52,6 +52,9 @@ int arch_cpu_init(void) #if defined(CONFIG_SPEAR_GPIO) periph1_clken |= MISC_GPIO3ENB | MISC_GPIO4ENB; #endif +#if defined(CONFIG_PL022_SPI) + periph1_clken |= MISC_SSP1ENB | MISC_SSP2ENB | MISC_SSP3ENB; +#endif
writel(periph1_clken, &misc_p->periph1_clken);
diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h index 65063fc..01b4b2b 100644 --- a/arch/arm/include/asm/arch-spear/spr_misc.h +++ b/arch/arm/include/asm/arch-spear/spr_misc.h @@ -146,11 +146,13 @@ struct misc_regs { #define MISC_SMIENB 0x00200000 #define MISC_GPIO3ENB 0x00040000 #define MISC_GPT3ENB 0x00010000 +#define MISC_SSP3ENB 0x00004000 #define MISC_GPIO4ENB 0x00002000 #define MISC_GPT2ENB 0x00000800 #define MISC_FSMCENB 0x00000200 #define MISC_I2CENB 0x00000080 #define MISC_SSP2ENB 0x00000070 +#define MISC_SSP1ENB 0x00000020 #define MISC_UART0ENB 0x00000008
/* PERIPH_CLK_CFG */