On Thursday, May 21, 2015 at 03:16:32 AM, Peng Fan wrote:
Hi Marek,
Hi!
On Wed, May 20, 2015 at 01:06:21PM +0200, Marek Vasut wrote:
On Wednesday, May 20, 2015 at 04:28:48 AM, Peng Fan wrote:
We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee that socs' cache line size is 32 bytes.
If on chips whose cache line size is 64 bytes, error occurs:
Which chips are those?
i.MX7's L1 Cache line size is 64 bytes.
Oh, I didn't know this was a public info. Oki, thanks for clarifying :)
NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 " Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.
Signed-off-by: Peng Fan Peng.Fan@freescale.com
Acked-by: Marek Vasut marex@denx.de
Best regards, Marek Vasut
Regards, Peng.
Best regards, Marek Vasut