In some part of STM32MP15 support the CONFIG_TFABOOT can be replaced by other config: CONFIG_ARMV7_PSCI and CONFIG_ARM_SMCCC.
This patch also simplifies the code in cpu.c, stm32mp1_ram.c and clk_stml32mp1.c as execution of U-Boot in sysram (boot without SPL and without TFA) is not supported: the associated initialization code is present only in SPL.
This cleanup patch is a preliminary step to support SPL load of OP-TEE in secure world, with SPL in secure world and U-Boot in no-secure world.
Reported-by: Alexandru Gagniuc mr.nuke.me@gmail.com Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com ---
arch/arm/mach-stm32mp/bsec.c | 10 +++++----- arch/arm/mach-stm32mp/cpu.c | 20 +++++++------------- board/st/stm32mp1/stm32mp1.c | 6 +++++- drivers/clk/clk_stm32mp1.c | 4 +--- drivers/ram/stm32mp1/stm32mp1_ram.c | 13 ++++++------- include/configs/stm32mp1.h | 2 +- 6 files changed, 25 insertions(+), 30 deletions(-)
diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index e517acdd01..27d1829501 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -295,7 +295,7 @@ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp) u32 tmp_data = 0; int ret;
- if (IS_ENABLED(CONFIG_TFABOOT)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) return stm32_smc(STM32_SMC_BSEC, STM32_SMC_READ_OTP, otp, 0, val); @@ -326,7 +326,7 @@ static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp) { struct stm32mp_bsec_plat *plat;
- if (IS_ENABLED(CONFIG_TFABOOT)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) return stm32_smc(STM32_SMC_BSEC, STM32_SMC_READ_SHADOW, otp, 0, val); @@ -350,7 +350,7 @@ static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp) { struct stm32mp_bsec_plat *plat;
- if (IS_ENABLED(CONFIG_TFABOOT)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_PROG_OTP, otp, val); @@ -365,7 +365,7 @@ static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp) { struct stm32mp_bsec_plat *plat;
- if (IS_ENABLED(CONFIG_TFABOOT)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_WRITE_SHADOW, otp, val); @@ -377,7 +377,7 @@ static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp) { - if (!IS_ENABLED(CONFIG_TFABOOT)) + if (!IS_ENABLED(CONFIG_ARM_SMCCC) || IS_ENABLED(CONFIG_SPL_BUILD)) return -ENOTSUPP;
if (val == 1) diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 0263ffe96a..7421ea42a1 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -93,8 +93,7 @@ u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
struct lmb lmb;
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) -#ifndef CONFIG_TFABOOT +#if defined(CONFIG_SPL_BUILD) static void security_init(void) { /* Disable the backup domain write protection */ @@ -154,7 +153,6 @@ static void security_init(void) writel(BIT(0), RCC_MP_AHB5ENSETR); writel(0x0, GPIOZ_SECCFGR); } -#endif /* CONFIG_TFABOOT */
/* * Debug init @@ -166,7 +164,7 @@ static void dbgmcu_init(void) * done in TF-A for TRUSTED boot and * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */ - if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) { + if (bsec_dbgswenable()) { setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); } @@ -184,10 +182,7 @@ void spl_board_init(void) if (ret) log_warning("BSEC probe failed: %d\n", ret); } -#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
-#if !defined(CONFIG_TFABOOT) && \ - (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) /* get bootmode from ROM code boot context: saved in TAMP register */ static void update_bootmode(void) { @@ -213,7 +208,7 @@ static void update_bootmode(void) TAMP_BOOT_MODE_MASK, boot_mode << TAMP_BOOT_MODE_SHIFT); } -#endif +#endif /* defined(CONFIG_SPL_BUILD) */
u32 get_bootmode(void) { @@ -291,11 +286,12 @@ int arch_cpu_init(void) /* early armv7 timer init: needed for polling */ timer_init();
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) -#ifndef CONFIG_TFABOOT +#if defined(CONFIG_SPL_BUILD) security_init(); update_bootmode(); #endif +/* reset copro state in SPL, when used, or in U-Boot */ +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) /* Reset Coprocessor state unless it wakes up from Standby power mode */ if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); @@ -308,9 +304,7 @@ int arch_cpu_init(void) if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; -#if defined(CONFIG_DEBUG_UART) && \ - !defined(CONFIG_TFABOOT) && \ - (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) +#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_SPL_BUILD) else debug_uart_init(); #endif diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 1d4d7b4b59..9391f483c5 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -664,7 +664,11 @@ int board_init(void) if (IS_ENABLED(CONFIG_DM_REGULATOR)) regulators_enable_boot_on(_DEBUG);
- if (!IS_ENABLED(CONFIG_TFABOOT)) + /* + * sysconf initialisation done only when U-Boot is running in secure + * done in TF-A for TFABOOT. + */ + if (IS_ENABLED(CONFIG_ARMV7_NONSEC)) sysconf_init();
if (CONFIG_IS_ENABLED(LED)) diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 114192bb32..83ab6b728e 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -27,12 +27,10 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_TFABOOT -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SPL_BUILD) /* activate clock tree initialization in the driver */ #define STM32MP1_CLOCK_TREE_INIT #endif -#endif
#define MAX_HSI_HZ 64000000
diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c index 26f0b4f1ea..98fa1f4f11 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ram.c +++ b/drivers/ram/stm32mp1/stm32mp1_ram.c @@ -202,17 +202,16 @@ static int stm32mp1_ddr_probe(struct udevice *dev)
priv->info.base = STM32_DDR_BASE;
-#if !defined(CONFIG_TFABOOT) && \ - (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) - priv->info.size = 0; - ret = stm32mp1_ddr_setup(dev); + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + priv->info.size = 0; + ret = stm32mp1_ddr_setup(dev); + + return log_ret(ret); + }
- return log_ret(ret); -#else ofnode node = stm32mp1_ddr_get_ofnode(dev); priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0); return 0; -#endif }
static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info) diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index 06cd153d13..f5c102a168 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -10,7 +10,7 @@ #include <linux/sizes.h> #include <asm/arch/stm32.h>
-#ifndef CONFIG_TFABOOT +#ifdef CONFIG_ARMV7_PSCI /* PSCI support */ #define CONFIG_ARMV7_SECURE_BASE STM32_SYSRAM_BASE #define CONFIG_ARMV7_SECURE_MAX_SIZE STM32_SYSRAM_SIZE