Enable support for NVMe storage devices. Update the driver to enable the bus master bit, since coreboot does not do that automatically.
Signed-off-by: Simon Glass sjg@chromium.org ---
(no changes since v2)
Changes in v2: - Drop patch 'usb: Quieten a debug message' since it was fixed elsewhere - Drop patch 'x86: coreboot: Use a memory-mapped UART' (not needed)
configs/coreboot_defconfig | 3 +++ drivers/nvme/nvme_pci.c | 8 ++++++++ 2 files changed, 11 insertions(+)
diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index 3030e5bf93b4..8bb744e6e84d 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -59,6 +59,9 @@ CONFIG_SYS_ATA_ALT_OFFSET=0 CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y +CONFIG_MISC=y +CONFIG_NVMEM=y +CONFIG_NVME_PCI=y # CONFIG_PCI_PNP is not set CONFIG_SOUND=y CONFIG_SOUND_I8254=y diff --git a/drivers/nvme/nvme_pci.c b/drivers/nvme/nvme_pci.c index 36bf9c5ffb73..dff19317943c 100644 --- a/drivers/nvme/nvme_pci.c +++ b/drivers/nvme/nvme_pci.c @@ -6,6 +6,7 @@
#include <common.h> #include <dm.h> +#include <init.h> #include <pci.h> #include "nvme.h"
@@ -30,6 +31,13 @@ static int nvme_probe(struct udevice *udev) ndev->instance = trailing_strtol(udev->name); ndev->bar = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM); + + if (!ll_boot_init()) { + /* Turn on bus-mastering */ + dm_pci_clrset_config16(udev, PCI_COMMAND, 0, + PCI_COMMAND_MASTER); + } + return nvme_init(udev); }