Partially sync with Linux's dts to add the entries required for USB3 support on USB0. Note that the default mode is still "peripheral" not "host". USB3 is supported only for the host mode.
Signed-off-by: Jean-Jacques Hiblot jjhiblot@ti.com Signed-off-by: Vignesh Raghavendra vigneshr@ti.com Signed-off-by: Kishon Vijay Abraham I kishon@ti.com --- .../k3-j721e-common-proc-board-u-boot.dtsi | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 3384ed9f3a..3b2e40c13d 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -115,13 +115,17 @@ u-boot,dm-spl; };
+&wiz3_pll1_refclk { + assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>; + assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>; +}; + &main_usbss0_pins_default { u-boot,dm-spl; };
&usbss0 { u-boot,dm-spl; - ti,usb2-only; };
&usb0 { @@ -193,3 +197,16 @@ &mcu_fss0_ospi1_pins_default { u-boot,dm-spl; }; + +&wiz3_pll1_refclk { + assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>; + assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>; +}; + +&serdes_ln_ctrl { + u-boot,mux-autoprobe; +}; + +&usb_serdes_mux { + u-boot,mux-autoprobe; +};