9 Apr
2013
9 Apr
'13
7:48 p.m.
Dear Scott Wood,
In message 1365450620.28843.12@snotra you wrote:
I thought you said it was OK to flush more than the user asked for, if the implementation does not have separate icache/dcache flushes? Why is it fundamentally different if it's a hardware limitation, or a limitation of the software layer whose functionality is being exposed?
I don't get what you are trying to prove. Can you please point me to the code (ideally in mainline U-Boot) which would cause problems with the suggested separation of invalidating the IC and flushing the DC into subcommands of the "icache" resp. "dcache" commands?
Best regards,
Wolfgang Denk
--
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