This board has not been converted to CONFIG_DM_MMC by the deadline of v2019.04, which is almost two years ago. In addition there are other DM migrations it is also missing. Remove it.
Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Cc: Priyanka Jain priyanka.jain@nxp.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/Kconfig | 13 --- arch/arm/cpu/armv8/Kconfig | 2 +- board/freescale/ls2080a/Kconfig | 35 ------ board/freescale/ls2080a/MAINTAINERS | 9 -- board/freescale/ls2080a/Makefile | 6 - board/freescale/ls2080a/README | 27 ----- board/freescale/ls2080a/ddr.c | 171 ---------------------------- board/freescale/ls2080a/ddr.h | 85 -------------- board/freescale/ls2080a/ls2080a.c | 147 ------------------------ configs/ls2080a_emu_defconfig | 38 ------- configs/ls2080a_simu_defconfig | 46 -------- drivers/i2c/Kconfig | 4 +- include/configs/ls2080a_emu.h | 80 ------------- include/configs/ls2080a_simu.h | 147 ------------------------ 14 files changed, 3 insertions(+), 807 deletions(-) delete mode 100644 board/freescale/ls2080a/Kconfig delete mode 100644 board/freescale/ls2080a/MAINTAINERS delete mode 100644 board/freescale/ls2080a/Makefile delete mode 100644 board/freescale/ls2080a/README delete mode 100644 board/freescale/ls2080a/ddr.c delete mode 100644 board/freescale/ls2080a/ddr.h delete mode 100644 board/freescale/ls2080a/ls2080a.c delete mode 100644 configs/ls2080a_emu_defconfig delete mode 100644 configs/ls2080a_simu_defconfig delete mode 100644 include/configs/ls2080a_emu.h delete mode 100644 include/configs/ls2080a_simu.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2e75efe2da8e..6263781e6f60 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1193,18 +1193,6 @@ config TARGET_LS2080A_EMU development platform that supports the QorIQ LS2080A Layerscape Architecture processor.
-config TARGET_LS2080A_SIMU - bool "Support ls2080a_simu" - select ARCH_LS2080A - select ARM64 - select ARMV8_MULTIENTRY - select BOARD_LATE_INIT - help - Support for Freescale LS2080A_SIMU platform. - The LS2080A Development System (QDS) is a pre silicon - development platform that supports the QorIQ LS2080A - Layerscape Architecture processor. - config TARGET_LS1088AQDS bool "Support ls1088aqds" select ARCH_LS1088A @@ -1962,7 +1950,6 @@ source "board/cavium/thunderx/Kconfig" source "board/cirrus/edb93xx/Kconfig" source "board/eets/pdu001/Kconfig" source "board/emulation/qemu-arm/Kconfig" -source "board/freescale/ls2080a/Kconfig" source "board/freescale/ls2080aqds/Kconfig" source "board/freescale/ls2080ardb/Kconfig" source "board/freescale/ls1088a/Kconfig" diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index f2474413ccab..9cd6a8d642b5 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -104,7 +104,7 @@ config PSCI_RESET default y select ARM_SMCCC if OF_CONTROL depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \ - !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \ + !TARGET_LS2080AQDS && \ !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \ !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \ !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \ diff --git a/board/freescale/ls2080a/Kconfig b/board/freescale/ls2080a/Kconfig deleted file mode 100644 index b5033511b55b..000000000000 --- a/board/freescale/ls2080a/Kconfig +++ /dev/null @@ -1,35 +0,0 @@ -if TARGET_LS2080A_EMU - -config SYS_BOARD - default "ls2080a" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls2080a_emu" - -source "board/freescale/common/Kconfig" - -endif - -if TARGET_LS2080A_SIMU - -config SYS_BOARD - default "ls2080a" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls2080a_simu" - -source "board/freescale/common/Kconfig" - -endif diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS deleted file mode 100644 index e0e4e3f83e89..000000000000 --- a/board/freescale/ls2080a/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -LS2080A BOARD -M: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com -M: Priyanka Jain priyanka.jain@nxp.com -S: Maintained -F: board/freescale/ls2080a/ -F: include/configs/ls2080a_emu.h -F: configs/ls2080a_emu_defconfig -F: include/configs/ls2080a_simu.h -F: configs/ls2080a_simu_defconfig diff --git a/board/freescale/ls2080a/Makefile b/board/freescale/ls2080a/Makefile deleted file mode 100644 index 87e26d977094..000000000000 --- a/board/freescale/ls2080a/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2014-15 Freescale Semiconductor - -obj-y += ls2080a.o -obj-y += ddr.o diff --git a/board/freescale/ls2080a/README b/board/freescale/ls2080a/README deleted file mode 100644 index 646cc02693bc..000000000000 --- a/board/freescale/ls2080a/README +++ /dev/null @@ -1,27 +0,0 @@ -Freescale ls2080a_emu - -This is a emulator target with limited peripherals. - -Memory map from core's view - -0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom -0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR -0x00_1800_0000 .. 0x00_181F_FFFF OCRAM -0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 -0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 -0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 -0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 - -Other addresses are either reserved, or not used directly by U-Boot. -This list should be updated when more addresses are used. - -Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) -------------------------------------------------------------------- -One needs to use appropriate bootargs to boot Linux flavors which do -not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown -below: - -=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram - earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m - hugepages=16 mem=2048M' - diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c deleted file mode 100644 index 229fc9cc30ea..000000000000 --- a/board/freescale/ls2080a/ddr.c +++ /dev/null @@ -1,171 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> -#include <log.h> -#include <asm/arch/soc.h> -#include <asm/arch/clock.h> -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 3) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - /* - * we use identical timing for all slots. If needed, change the code - * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; - */ - if (popts->registered_dimm_en) - pbsp = rdimms[ctrl_num]; - else - pbsp = udimms[ctrl_num]; - - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks && - (pdimm->rank_density >> 30) >= pbsp->rank_gb) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for data rate %lu MT/s\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" - "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, - pbsp->wrlvl_ctl_3); -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (ctrl_num == CONFIG_DP_DDR_CTRL) { - /* force DDR bus width to 32 bits */ - popts->data_bus_width = 1; - popts->otf_burst_chop_en = 0; - popts->burst_length = DDR_BL8; - popts->bstopre = 0; /* enable auto precharge */ - } -#endif - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 1; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - -#ifdef CONFIG_SYS_FSL_DDR4 - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | - DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ -#else - /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); -#endif -} - -#ifdef CONFIG_SYS_DDR_RAW_TIMING -dimm_params_t ddr_raw_timing = { - .n_ranks = 2, - .rank_density = 1073741824u, - .capacity = 2147483648, - .primary_sdram_width = 64, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 14, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 937, - .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */ - .taa_ps = 13090, - .twr_ps = 15000, - .trcd_ps = 13090, - .trrd_ps = 5000, - .trp_ps = 13090, - .tras_ps = 33000, - .trc_ps = 46090, - .trfc_ps = 160000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 25000, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - const char dimm_model[] = "Fixed DDR on board"; - - if (((controller_number == 0) && (dimm_number == 0)) || - ((controller_number == 1) && (dimm_number == 0))) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} -#endif - -int fsl_initdram(void) -{ - puts("Initializing DDR...."); - - puts("using SPD\n"); - gd->ram_size = fsl_ddr_sdram(); - - return 0; -} diff --git a/board/freescale/ls2080a/ddr.h b/board/freescale/ls2080a/ddr.h deleted file mode 100644 index d21b9265586d..000000000000 --- a/board/freescale/ls2080a/ddr.h +++ /dev/null @@ -1,85 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ - -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 2140, 0, 4, 4, 0x0, 0x0}, - {1, 2140, 0, 4, 4, 0x0, 0x0}, - {} -}; - -/* DP-DDR DIMM */ -static const struct board_specific_parameters udimm2[] = { - /* - * memory controller 2 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 2140, 0, 4, 4, 0x0, 0x0}, - {1, 2140, 0, 4, 4, 0x0, 0x0}, - {} -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {4, 2140, 0, 5, 4, 0x0, 0x0}, - {2, 2140, 0, 5, 4, 0x0, 0x0}, - {1, 2140, 0, 4, 4, 0x0, 0x0}, - {} -}; - -/* DP-DDR DIMM */ -static const struct board_specific_parameters rdimm2[] = { - /* - * memory controller 2 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {4, 2140, 0, 5, 4, 0x0, 0x0}, - {2, 2140, 0, 5, 4, 0x0, 0x0}, - {1, 2140, 0, 4, 4, 0x0, 0x0}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, - udimm0, - udimm2, -}; - -static const struct board_specific_parameters *rdimms[] = { - rdimm0, - rdimm0, - rdimm2, -}; - - -#endif diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c deleted file mode 100644 index 62da2a7af11a..000000000000 --- a/board/freescale/ls2080a/ls2080a.c +++ /dev/null @@ -1,147 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor - */ -#include <common.h> -#include <init.h> -#include <malloc.h> -#include <errno.h> -#include <net.h> -#include <netdev.h> -#include <fsl_ifc.h> -#include <fsl_ddr.h> -#include <asm/io.h> -#include <fdt_support.h> -#include <linux/libfdt.h> -#include <fsl-mc/fsl_mc.h> -#include <env_internal.h> -#include <asm/arch/soc.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - init_final_memctl_regs(); - -#ifdef CONFIG_ENV_IS_NOWHERE - gd->env_addr = (ulong)&default_environment[0]; -#endif - - return 0; -} - -int board_early_init_f(void) -{ - fsl_lsch3_early_init_f(); - return 0; -} - -void detail_board_ddr_info(void) -{ - puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); - print_ddr_info(0); -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { - puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); - print_ddr_info(CONFIG_DP_DDR_CTRL); - } -#endif -} - -int board_eth_init(struct bd_info *bis) -{ - int error = 0; - -#ifdef CONFIG_SMC91111 - error = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) - error = cpu_eth_init(bis); -#endif - return error; -} - -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) -void fdt_fixup_board_enet(void *fdt) -{ - int offset; - - offset = fdt_path_offset(fdt, "/soc/fsl-mc"); - - /* - * TODO: Remove this when backward compatibility - * with old DT node (/fsl-mc) is no longer needed. - */ - if (offset < 0) - offset = fdt_path_offset(fdt, "/fsl-mc"); - - if (offset < 0) { - printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", - __func__, offset); - return; - } - - if (get_mc_boot_status() == 0 && - (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) - fdt_status_okay(fdt, offset); - else - fdt_status_fail(fdt, offset); -} - -void board_quiesce_devices(void) -{ - fsl_mc_ldpaa_exit(gd->bd); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - - ft_cpu_setup(blob, bd); - - /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; - -#ifdef CONFIG_RESV_RAM - /* reduce size if reserved memory is within this bank */ - if (gd->arch.resv_ram >= base[0] && - gd->arch.resv_ram < base[0] + size[0]) - size[0] = gd->arch.resv_ram - base[0]; - else if (gd->arch.resv_ram >= base[1] && - gd->arch.resv_ram < base[1] + size[1]) - size[1] = gd->arch.resv_ram - base[1]; -#endif - - fdt_fixup_memory_banks(blob, base, size, 2); - - fdt_fsl_mc_fixup_iommu_map_entry(blob); - -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) - fdt_fixup_board_enet(blob); -#endif - - return 0; -} -#endif - -#if defined(CONFIG_RESET_PHY_R) -void reset_phy(void) -{ -} -#endif - -#ifdef CONFIG_TFABOOT -void *env_sf_get_env_addr(void) -{ - return (void *)(CONFIG_SYS_FSL_QSPI_BASE1 + CONFIG_ENV_OFFSET); -} -#endif diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig deleted file mode 100644 index c42f012a6a29..000000000000 --- a/configs/ls2080a_emu_defconfig +++ /dev/null @@ -1,38 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS2080A_EMU=y -CONFIG_SYS_TEXT_BASE=0x30100000 -CONFIG_NR_DRAM_BANKS=3 -CONFIG_ENV_SIZE=0x1000 -CONFIG_IDENT_STRING=" LS2080A-EMU" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="EMU" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" -# CONFIG_USE_BOOTCOMMAND is not set -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -CONFIG_CMD_CACHE=y -# CONFIG_CMD_SLEEP is not set -CONFIG_MP=y -# CONFIG_DOS_PARTITION is not set -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -# CONFIG_MMC is not set -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig deleted file mode 100644 index 2aabb772079d..000000000000 --- a/configs/ls2080a_simu_defconfig +++ /dev/null @@ -1,46 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS2080A_SIMU=y -CONFIG_SYS_TEXT_BASE=0x30100000 -CONFIG_NR_DRAM_BANKS=3 -CONFIG_ENV_SIZE=0x1000 -CONFIG_IDENT_STRING=" LS2080A-SIMU" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SIMU" -CONFIG_BOOTDELAY=10 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256" -# CONFIG_USE_BOOTCOMMAND is not set -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -CONFIG_CMD_CACHE=y -# CONFIG_CMD_SLEEP is not set -CONFIG_MP=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 367004b15bc7..ec3d6779dfbb 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -222,7 +222,7 @@ endif if SYS_I2C_MXC_I2C1 config SYS_MXC_I2C1_SPEED int "I2C Channel 1 speed" - default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU + default 40000000 if TARGET_LS2080A_EMU default 100000 help MXC I2C Channel 1 speed @@ -237,7 +237,7 @@ endif if SYS_I2C_MXC_I2C2 config SYS_MXC_I2C2_SPEED int "I2C Channel 2 speed" - default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU + default 40000000 if TARGET_LS2080A_EMU default 100000 help MXC I2C Channel 2 speed diff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h deleted file mode 100644 index 3e0ad48ddacc..000000000000 --- a/include/configs/ls2080a_emu.h +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor - */ - -#ifndef __LS2_EMU_H -#define __LS2_EMU_H - -#include "ls2080a_common.h" - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 133333333 - -#define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */ -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x52 -#define SPD_EEPROM_ADDRESS3 0x53 -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */ -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 -#endif - -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -/* - * NOR Flash Timing Params - */ -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ - FTIM0_NOR_TEADC(0x1) | \ - FTIM0_NOR_TEAHC(0x1)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ - FTIM1_NOR_TRAD_NOR(0x1)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ - FTIM2_NOR_TCH(0x0) | \ - FTIM2_NOR_TWP(0x1)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 - -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 - -/* Debug Server firmware */ -#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR -#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL - -/* - * This trick allows users to load MC images into DDR directly without - * copying from NOR flash. It dramatically improves speed. - */ -#define CONFIG_SYS_LS_MC_FW_IN_DDR -#define CONFIG_SYS_LS_MC_DPL_IN_DDR -#define CONFIG_SYS_LS_MC_DPC_IN_DDR - -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000 - -/* Store environment at top of flash */ - -#endif /* __LS2_EMU_H */ diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h deleted file mode 100644 index ab46df76007f..000000000000 --- a/include/configs/ls2080a_simu.h +++ /dev/null @@ -1,147 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Freescale Semiconductor - */ - -#ifndef __LS2_SIMU_H -#define __LS2_SIMU_H - -#include "ls2080a_common.h" - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 133333333 - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 -#endif - -/* SMSC 91C111 ethernet configuration */ -#define CONFIG_SMC91111 -#define CONFIG_SMC91111_BASE (0x2210000) - -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) - -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_QUIET_TEST -#endif - -/* - * NOR Flash Timing Params - */ -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ - FTIM0_NOR_TEADC(0x1) | \ - FTIM0_NOR_TEAHC(0x1)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ - FTIM1_NOR_TRAD_NOR(0x1)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ - FTIM2_NOR_TCH(0x0) | \ - FTIM2_NOR_TWP(0x1)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 - -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#endif - -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 - -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - -/* Debug Server firmware */ -#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR -#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL - -/* MC firmware */ -#define CONFIG_SYS_LS_MC_DPL_IN_NOR -#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL - -#define CONFIG_SYS_LS_MC_DPC_IN_NOR -#define CONFIG_SYS_LS_MC_DPC_ADDR 0x5806F8000ULL - -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000 - -/* Store environment at top of flash */ - -#endif /* __LS2_SIMU_H */