Reset the GMAC ethernets based on the "resets" OF node instead of ad-hoc hardcoded values in the U-Boot code. Since we don't have a proper reset framework in place yet, we have to do this slightly ad-hoc parsing of the OF tree instead.
Signed-off-by: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Joe Hershberger joe.hershberger@ni.com --- arch/arm/mach-socfpga/misc.c | 68 +++++++++++++++++++++++++++----------- include/configs/socfpga_arria5.h | 1 - include/configs/socfpga_cyclone5.h | 1 - include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 5 files changed, 51 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 4b1c052..9d34cd3 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -6,6 +6,8 @@
#include <common.h> #include <asm/io.h> +#include <fdtdec.h> +#include <libfdt.h> #include <altera.h> #include <miiphy.h> #include <netdev.h> @@ -17,6 +19,8 @@ #include <asm/arch/scu.h> #include <asm/pl310.h>
+#include <dt-bindings/reset/altr,rst-mgr.h> + DECLARE_GLOBAL_DATA_PTR;
static struct pl310_regs *const pl310 = @@ -50,26 +54,20 @@ void enable_caches(void) * DesignWare Ethernet initialization */ #ifdef CONFIG_ETH_DESIGNWARE -int cpu_eth_init(bd_t *bis) +static void dwmac_deassert_reset(const unsigned int of_reset_id) { -#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS - const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; - const u32 reset = SOCFPGA_RESET(EMAC0); -#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS - const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; - const u32 reset = SOCFPGA_RESET(EMAC1); -#else -#error "Incorrect CONFIG_EMAC_BASE value!" -#endif - - /* Initialize EMAC. This needs to be done at least once per boot. */ - - /* - * Putting the EMAC controller to reset when configuring the PHY - * interface select at System Manager - */ - socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); - socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); + u32 physhift, reset; + + if (of_reset_id == EMAC0_RESET) { + physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; + reset = SOCFPGA_RESET(EMAC0); + } else if (of_reset_id == EMAC1_RESET) { + physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; + reset = SOCFPGA_RESET(EMAC1); + } else { + printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); + return; + }
/* Clearing emac0 PHY interface select to 0 */ clrbits_le32(&sysmgr_regs->emacgrp_ctrl, @@ -81,6 +79,38 @@ int cpu_eth_init(bd_t *bis)
/* Release the EMAC controller from reset */ socfpga_per_reset(reset, 0); +} + +int cpu_eth_init(bd_t *bis) +{ + const void *fdt = gd->fdt_blob; + struct fdtdec_phandle_args args; + int nodes[2]; /* Max. two GMACs */ + int ret, count; + int i, node; + + /* Put both GMACs into RESET state. */ + socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); + socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); + + count = fdtdec_find_aliases_for_id(fdt, "ethernet", + COMPAT_ALTERA_SOCFPGA_DWMAC, + nodes, ARRAY_SIZE(nodes)); + for (i = 0; i < count; i++) { + node = nodes[i]; + if (node <= 0) + continue; + + ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", + "#reset-cells", 1, 0, + &args); + if (ret || (args.args_count != 1)) { + debug("GMAC%i: Failed to parse DT 'resets'!\n", i); + continue; + } + + dwmac_deassert_reset(args.args[0]); + }
return 0; } diff --git a/include/configs/socfpga_arria5.h b/include/configs/socfpga_arria5.h index d8f2438..ed865ce 100644 --- a/include/configs/socfpga_arria5.h +++ b/include/configs/socfpga_arria5.h @@ -48,7 +48,6 @@
/* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) -#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
/* PHY */ #define CONFIG_PHY_MICREL diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index a27660e..f13ed3e 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -48,7 +48,6 @@
/* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) -#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
/* PHY */ #define CONFIG_PHY_MICREL diff --git a/include/fdtdec.h b/include/fdtdec.h index 1a39b9f..fdac3cd 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -184,6 +184,7 @@ enum fdt_compat_id { COMPAT_INTEL_PCH, /* Intel PCH */ COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */ COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */ + COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */
COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index d0f81bc..c1f40eb 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -77,6 +77,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"), COMPAT(COMPAT_INTEL_IRQ_ROUTER, "intel,irq-router"), COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"), + COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"), };
const char *fdtdec_get_compatible(enum fdt_compat_id id)