As per dwc3 databook, delay is required before taking the core out of reset. This delay is required so that the PHY are stable, and then we can take core out of reset.
Reference is taken from linux dwc3 code, file: drivers/usb/dwc3/core.c.
Signed-off-by: Sriram Dash sriram.dash@freescale.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@freescale.com --- drivers/usb/host/xhci-dwc3.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index c722c50..33961cd 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -44,6 +44,8 @@ void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) /* reset USB3 phy - if required */ dwc3_phy_reset(dwc3_reg);
+ mdelay(100); + /* After PHYs are stable we can take Core out of reset state */ clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); }