6 Aug
2016
6 Aug
'16
6:59 p.m.
On Sat, Aug 06, 2016 at 02:00:39AM +0300, Max Filippov wrote:
From: Chris Zankel chris@zankel.net
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Cadence.
This is the first part of the basic architecture port with changes to common files. The 'arch/xtensa' directory, and boards and additional drivers will be in separate commits.
Signed-off-by: Chris Zankel chris@zankel.net Signed-off-by: Max Filippov jcmvbkbc@gmail.com
Reviewed-by: Tom Rini trini@konsulko.com
--
Tom