Add 8M for the U-Boot reserved memory (display, fdt, gd, ...) mapped cacheable before relocation.
Without this patch the device tree, located before the MALLOC area is not tagged cacheable just after relocation, before mmu reconfiguration.
This patch reduces the duration for device tree parsing in lmb_init_and_reserve.
Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com ---
Changes in v4: - map the end of the DDR only before relocation, in board_f.c; this test avoid issue when board_get_usable_ram_top() is called in efi_loader function efi_add_known_memory()
Changes in v3: - NEW: solve performance issue as relocated DT is not marked cacheable
arch/arm/mach-stm32mp/dram_init.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 66e81bacca..3c097029bd 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -50,13 +50,16 @@ ulong board_get_usable_ram_top(ulong total_size) lmb_init(&lmb); lmb_add(&lmb, gd->ram_base, gd->ram_size); boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob); - size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE), + /* add 8M for reserved memory for display, fdt, gd,... */ + size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE), reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
if (!reg) reg = gd->ram_top - size;
- mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION); + /* before relocation, mark the U-Boot memory as cacheable by default */ + if (!(gd->flags & GD_FLG_RELOC)) + mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION);
return reg + size; }