Commit c7190f02 (retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields) moved the LCRR assignment to after relocation to RAM because of the potential problem with changing the local bus clock while executing from flash.
For some boards this isn't needed (E.G. when running from a normal async NOR flash), and running all code up to cpu_init_r at the slow bootup speed adversively affects the startup time.
E.G. on a 8347 board a bootup time increase of ~600ms has been observed:
0.020 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz 0.168 RS: 232 0.172 I2C: ready 0.176 DRAM: 64 MB 1.236 FLASH: 32 MB
Versus:
0.016 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz 0.092 RS: 232 0.092 I2C: ready 0.096 DRAM: 64 MB 0.644 FLASH: 32 MB
Fix it by introducing CONFIG_SYS_LCRR_EARLY, and set LCRR in cpu_init_f instead of in cpu_init_r if set.
Signed-off-by: Peter Korsgaard jacmet@sunsite.dk --- cpu/mpc83xx/cpu_init.c | 35 +++++++++++++++++++++++++++++++++++ 1 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 031e8d5..ef4d694 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -171,6 +171,30 @@ void cpu_init_f (volatile immap_t * im) (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) | #endif 0; +#ifdef CONFIG_SYS_LCRR_EARLY + __be32 lcrr_mask = +#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */ + LCRR_DBYP | +#endif +#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */ + LCRR_EADC | +#endif +#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */ + LCRR_CLKDIV | +#endif + 0; + __be32 lcrr_val = +#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */ + CONFIG_SYS_LCRR_DBYP | +#endif +#ifdef CONFIG_SYS_LCRR_EADC + CONFIG_SYS_LCRR_EADC | +#endif +#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */ + CONFIG_SYS_LCRR_CLKDIV | +#endif + 0; +#endif /* CONFIG_SYS_LCRR_EARLY */
/* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); @@ -199,6 +223,15 @@ void cpu_init_f (volatile immap_t * im) */ __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
+#ifdef CONFIG_SYS_LCRR_EARLY + /* LCRR - Clock Ratio Register (10.3.1.16) + * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description + */ + clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val); + __raw_readl(&im->lbus.lcrr); + isync(); +#endif + /* Enable Time Base & Decrementer ( so we will have udelay() )*/ setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
@@ -335,6 +368,7 @@ int cpu_init_r (void) #ifdef CONFIG_QE uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */ #endif +#ifndef CONFIG_SYS_LCRR_EARLY __be32 lcrr_mask = #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */ LCRR_DBYP | @@ -364,6 +398,7 @@ int cpu_init_r (void) clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val); __raw_readl(&im->lbus.lcrr); isync(); +#endif /* !CONFIG_SYS_LCRR_EARLY */
#ifdef CONFIG_QE qe_init(qe_base);