Hi Tudor,
-----Original Message----- From: Tudor Ambarus tudor.ambarus@linaro.org Sent: Monday, November 25, 2024 12:59 PM To: Abbarapu, Venkatesh venkatesh.abbarapu@amd.com; u-boot@lists.denx.de; j-humphreys@ti.com Cc: Simek, Michal michal.simek@amd.com; jagan@amarulasolutions.com; vigneshr@ti.com; u-kumar1@ti.com; trini@konsulko.com; seanga2@gmail.com; caleb.connolly@linaro.org; sjg@chromium.org; william.zhang@broadcom.com; stefan_b@posteo.net; quentin.schulz@cherry.de; Takahiro.Kuwano@infineon.com; git (AMD-Xilinx) git@amd.com; Tejas Bhumkar tejas.arvind.bhumkar@amd.com; Dragan Simic dsimic@manjaro.org Subject: Re: [PATCH] mtd: spi-nor: Add support for Macronix flash part
Hi,
On 11/22/24 9:47 AM, Venkatesh Yadav Abbarapu wrote:
Added support for Macronix OSPI flash parts MX25UM51345G and MX66UM2G45G, with initial testing conducted on the Tenzing-se1 board using STR mode for basic erase, write, and readback operations.
Signed-off-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com Signed-off-by: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com Reviewed-by: Dragan Simic dsimic@manjaro.org
drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 91ae49c948..a130845d41 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -275,6 +275,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32,
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
{ INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) },
- { INFO("mx25um51345g", 0xc2813a, 0, 64 * 1024, 1024, SECT_4K |
SPI_NOR_4B_OPCODES) },
- { INFO("mx66um2g45g", 0xc2803c, 0, 64 * 1024, 4096, SECT_4K |
SPI_NOR_4B_OPCODES) },
Do these flashes support SFDP? If yes, are the SECT_4K | SPI_NOR_4B_OPCODES flags really needed?
The config SPI_FLASH_SFDP_SUPPORT is not enabled in our case, so adding these flags.
Thanks Venkatesh
Cheers, ta
{ INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K |
SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_READ) },
{ INFO("mx66lm1g45g", 0xc2853b, 0, 64 * 1024, 2048, SECT_4K |
SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25lm51245g", 0xc2853a, 0, 64 * 1024, 1024, SECT_4K |
SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },