The mul and div arguments were reported in reverse order in the debug message, swap them to fix this.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- drivers/clk/renesas/clk-rcar-gen3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 3a95647abe..4f10fd6352 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -230,7 +230,7 @@ static ulong gen3_clk_get_rate(struct clk *clk) case CLK_TYPE_FF: case CLK_TYPE_GEN3_PE: /* FIXME */ rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div; - debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n", + debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n", __func__, __LINE__, core->parent, core->mult, core->div, rate); return rate;