Add a bare-bones CPU driver so that CPUs can be probed.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v6: - Drop unnecessary priv struct and probe method - Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option
Changes in v5: - Add L2 cache flush function - Drop SAFETY_MARGIN
Changes in v4: - Change apollolake to apl - Tidy up header guards
Changes in v3: - Add two more defines for the CPU driver - Expand comments for BOOT_FROM_FAST_SPI_FLASH
Changes in v2: None
arch/x86/cpu/apollolake/Makefile | 2 ++ arch/x86/cpu/apollolake/cpu.c | 41 ++++++++++++++++++++++ arch/x86/cpu/apollolake/cpu_common.c | 17 +++++++++ arch/x86/include/asm/arch-apollolake/cpu.h | 20 +++++++++++ arch/x86/include/asm/msr-index.h | 1 + 5 files changed, 81 insertions(+) create mode 100644 arch/x86/cpu/apollolake/cpu.c create mode 100644 arch/x86/cpu/apollolake/cpu_common.c create mode 100644 arch/x86/include/asm/arch-apollolake/cpu.h
diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 1fde400d77..37e42092ec 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -4,8 +4,10 @@
obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_SPL_BUILD) += systemagent.o +obj-y += cpu_common.o
ifndef CONFIG_TPL_BUILD +obj-y += cpu.o obj-y += punit.o endif
diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c new file mode 100644 index 0000000000..3d05c82a5c --- /dev/null +++ b/arch/x86/cpu/apollolake/cpu.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + */ + +#include <common.h> +#include <cpu.h> +#include <dm.h> +#include <asm/cpu_common.h> +#include <asm/cpu_x86.h> + +static int apl_get_info(struct udevice *dev, struct cpu_info *info) +{ + return cpu_intel_get_info(info, INTEL_BCLK_MHZ); +} + +static int apl_get_count(struct udevice *dev) +{ + return 4; +} + +static const struct cpu_ops cpu_x86_apl_ops = { + .get_desc = cpu_x86_get_desc, + .get_info = apl_get_info, + .get_count = apl_get_count, + .get_vendor = cpu_x86_get_vendor, +}; + +static const struct udevice_id cpu_x86_apl_ids[] = { + { .compatible = "intel,apl-cpu" }, + { } +}; + +U_BOOT_DRIVER(cpu_x86_apl_drv) = { + .name = "cpu_x86_apl", + .id = UCLASS_CPU, + .of_match = cpu_x86_apl_ids, + .bind = cpu_x86_bind, + .ops = &cpu_x86_apl_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/arch/x86/cpu/apollolake/cpu_common.c b/arch/x86/cpu/apollolake/cpu_common.c new file mode 100644 index 0000000000..ba6bda37bc --- /dev/null +++ b/arch/x86/cpu/apollolake/cpu_common.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + */ + +#include <common.h> +#include <asm/cpu_common.h> +#include <asm/msr.h> + +void cpu_flush_l1d_to_l2(void) +{ + struct msr_t msr; + + msr = msr_read(MSR_POWER_MISC); + msr.lo |= FLUSH_DL1_L2; + msr_write(MSR_POWER_MISC, msr); +} diff --git a/arch/x86/include/asm/arch-apollolake/cpu.h b/arch/x86/include/asm/arch-apollolake/cpu.h new file mode 100644 index 0000000000..5e906c5e7d --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/cpu.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef _ASM_ARCH_CPU_H +#define _ASM_ARCH_CPU_H + +/* Common Timer Copy (CTC) frequency - 19.2MHz */ +#define CTC_FREQ 19200000 + +#define MAX_PCIE_PORTS 6 +#define CLKREQ_DISABLED 0xf + +#ifndef __ASSEMBLY__ +/* Flush L1D to L2 */ +void cpu_flush_l1d_to_l2(void); +#endif + +#endif /* _ASM_ARCH_CPU_H */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 79a9369de1..246c14f815 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -70,6 +70,7 @@ #define MSR_IA32_BBL_CR_CTL 0x00000119 #define MSR_IA32_BBL_CR_CTL3 0x0000011e #define MSR_POWER_MISC 0x00000120 +#define FLUSH_DL1_L2 (1 << 8) #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) #define ENABLE_INDP_AUTOCM_MASK (1 << 3)