Move this field into arch_global_data and tidy up.
Signed-off-by: Simon Glass sjg@chromium.org --- arch/powerpc/cpu/mpc8260/commproc.c | 2 +- arch/powerpc/cpu/mpc8260/i2c.c | 2 +- arch/powerpc/cpu/mpc8260/speed.c | 4 ++-- arch/powerpc/cpu/mpc83xx/speed.c | 5 +++-- arch/powerpc/cpu/mpc85xx/commproc.c | 2 +- arch/powerpc/cpu/mpc85xx/speed.c | 4 ++-- arch/powerpc/cpu/mpc8xx/fdt.c | 2 +- arch/powerpc/cpu/mpc8xx/speed.c | 2 +- arch/powerpc/include/asm/global_data.h | 14 +++++++++----- arch/powerpc/lib/board.c | 2 +- common/cmd_immap.c | 2 +- drivers/qe/fdt.c | 4 ++-- drivers/qe/qe.c | 2 +- 13 files changed, 26 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8260/commproc.c b/arch/powerpc/cpu/mpc8260/commproc.c index 082957e..e5bfed1 100644 --- a/arch/powerpc/cpu/mpc8260/commproc.c +++ b/arch/powerpc/cpu/mpc8260/commproc.c @@ -101,7 +101,7 @@ m8260_cpm_hostalloc(uint size, uint align) * Baud rate clocks are zero-based in the driver code (as that maps * to port numbers). Documentation uses 1-based numbering. */ -#define BRG_INT_CLK gd->brg_clk +#define BRG_INT_CLK gd->arch.brg_clk #define BRG_UART_CLK (BRG_INT_CLK / 16)
/* This function is used by UARTs, or anything else that uses a 16x diff --git a/arch/powerpc/cpu/mpc8260/i2c.c b/arch/powerpc/cpu/mpc8260/i2c.c index 7382cba..b720b1f 100644 --- a/arch/powerpc/cpu/mpc8260/i2c.c +++ b/arch/powerpc/cpu/mpc8260/i2c.c @@ -259,7 +259,7 @@ void i2c_init(int speed, int slaveadd) * divide BRGCLK by 1) */ debug("[I2C] Setting rate...\n"); - i2c_setrate(gd->brg_clk, CONFIG_SYS_I2C_SPEED); + i2c_setrate(gd->arch.brg_clk, CONFIG_SYS_I2C_SPEED);
/* Set I2C controller in master mode */ i2c->i2c_i2com = 0x01; diff --git a/arch/powerpc/cpu/mpc8260/speed.c b/arch/powerpc/cpu/mpc8260/speed.c index bb50dee..4ad1ec2 100644 --- a/arch/powerpc/cpu/mpc8260/speed.c +++ b/arch/powerpc/cpu/mpc8260/speed.c @@ -145,7 +145,7 @@ int get_clocks (void) gd->cpm_clk = gd->vco_out / 2; gd->bus_clk = clkin; gd->scc_clk = gd->vco_out / 4; - gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1))); + gd->arch.brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
if (cp->b2c_mult > 0) { gd->cpu_clk = (clkin * cp->b2c_mult) / 2; @@ -231,7 +231,7 @@ int prt_8260_clks (void) plldf, pllmf, pcidf);
printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n", - gd->vco_out, gd->scc_clk, gd->brg_clk); + gd->vco_out, gd->scc_clk, gd->arch.brg_clk);
printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n", gd->cpu_clk, gd->cpm_clk, gd->bus_clk); diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index b8c05d1..21e8b0a 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -496,7 +496,7 @@ int get_clocks(void) #endif #if defined(CONFIG_QE) gd->qe_clk = qe_clk; - gd->brg_clk = brg_clk; + gd->arch.brg_clk = brg_clk; #endif #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) @@ -540,7 +540,8 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk)); #if defined(CONFIG_QE) printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk)); - printf(" BRG: %-4s MHz\n", strmhz(buf, gd->brg_clk)); + printf(" BRG: %-4s MHz\n", + strmhz(buf, gd->arch.brg_clk)); #endif printf(" Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk)); printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->lclk_clk)); diff --git a/arch/powerpc/cpu/mpc85xx/commproc.c b/arch/powerpc/cpu/mpc85xx/commproc.c index 292b723..7f10476 100644 --- a/arch/powerpc/cpu/mpc85xx/commproc.c +++ b/arch/powerpc/cpu/mpc85xx/commproc.c @@ -110,7 +110,7 @@ m8560_cpm_hostalloc(uint size, uint align) * Baud rate clocks are zero-based in the driver code (as that maps * to port numbers). Documentation uses 1-based numbering. */ -#define BRG_INT_CLK gd->brg_clk +#define BRG_INT_CLK gd->arch.brg_clk #define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16)
/* This function is used by UARTS, or anything else that uses a 16x diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 801ee07..8a581ef 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -395,7 +395,7 @@ int get_clocks (void)
#ifdef CONFIG_QE gd->qe_clk = sys_info.freqQE; - gd->brg_clk = gd->qe_clk / 2; + gd->arch.brg_clk = gd->qe_clk / 2; #endif /* * The base clock for I2C depends on the actual SOC. Unfortunately, @@ -438,7 +438,7 @@ int get_clocks (void) gd->vco_out = 2*sys_info.freqSystemBus; gd->cpm_clk = gd->vco_out / 2; gd->scc_clk = gd->vco_out / 4; - gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1))); + gd->arch.brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1))); #endif
if(gd->cpu_clk != 0) return (0); diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c index 7130983..7edd7e4 100644 --- a/arch/powerpc/cpu/mpc8xx/fdt.c +++ b/arch/powerpc/cpu/mpc8xx/fdt.c @@ -37,7 +37,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", bd->bi_intfreq, 1); do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency", - gd->brg_clk, 1); + gd->arch.brg_clk, 1);
/* Fixup ethernet MAC addresses */ fdt_fixup_ethernet(blob); diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c index 6e13e5d..091b49f 100644 --- a/arch/powerpc/cpu/mpc8xx/speed.c +++ b/arch/powerpc/cpu/mpc8xx/speed.c @@ -192,7 +192,7 @@ void get_brgclk(uint sccr) divider = 64; break; } - gd->brg_clk = gd->cpu_clk/divider; + gd->arch.brg_clk = gd->cpu_clk/divider; }
#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index df621da..ac348c6 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -29,6 +29,15 @@
/* Architecture-specific global data */ struct arch_global_data { +#if defined(CONFIG_8xx) + unsigned long brg_clk; +#endif +#if defined(CONFIG_CPM2) + unsigned long brg_clk; +#endif +#if defined(CONFIG_QE) + u32 brg_clk; +#endif };
/* @@ -45,15 +54,11 @@ typedef struct global_data { unsigned int baudrate; unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; -#if defined(CONFIG_8xx) - unsigned long brg_clk; -#endif #if defined(CONFIG_CPM2) /* There are many clocks on the MPC8260 - see page 9-5 */ unsigned long vco_out; unsigned long cpm_clk; unsigned long scc_clk; - unsigned long brg_clk; #ifdef CONFIG_PCI unsigned long pci_clk; #endif @@ -106,7 +111,6 @@ typedef struct global_data { #endif #if defined(CONFIG_QE) u32 qe_clk; - u32 brg_clk; uint mp_alloc_base; uint mp_alloc_top; #endif /* CONFIG_QE */ diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 1b051e1..4174a73 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -581,7 +581,7 @@ void board_init_f(ulong bootflag) bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ #if defined(CONFIG_CPM2) bd->bi_cpmfreq = gd->cpm_clk; - bd->bi_brgfreq = gd->brg_clk; + bd->bi_brgfreq = gd->arch.brg_clk; bd->bi_sccfreq = gd->scc_clk; bd->bi_vco = gd->vco_out; #endif /* CONFIG_CPM2 */ diff --git a/common/cmd_immap.c b/common/cmd_immap.c index 1f59c1e..fdf9489 100644 --- a/common/cmd_immap.c +++ b/common/cmd_immap.c @@ -453,7 +453,7 @@ static void prbrg (int n, uint val) #if defined(CONFIG_8xx) ulong clock = gd->cpu_clk; #elif defined(CONFIG_8260) - ulong clock = gd->brg_clk; + ulong clock = gd->arch.brg_clk; #endif
printf ("BRG%d:", n); diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c index 73e9060..1a123b8 100644 --- a/drivers/qe/fdt.c +++ b/drivers/qe/fdt.c @@ -77,13 +77,13 @@ void ft_qe_setup(void *blob) do_fixup_by_prop_u32(blob, "device_type", "qe", 4, "bus-frequency", gd->qe_clk, 1); do_fixup_by_prop_u32(blob, "device_type", "qe", 4, - "brg-frequency", gd->brg_clk, 1); + "brg-frequency", gd->arch.brg_clk, 1); do_fixup_by_compat_u32(blob, "fsl,qe", "clock-frequency", gd->qe_clk, 1); do_fixup_by_compat_u32(blob, "fsl,qe", "bus-frequency", gd->qe_clk, 1); do_fixup_by_compat_u32(blob, "fsl,qe", - "brg-frequency", gd->brg_clk, 1); + "brg-frequency", gd->arch.brg_clk, 1); do_fixup_by_compat_u32(blob, "fsl,qe-gtm", "clock-frequency", gd->qe_clk / 2, 1); fdt_fixup_qe_firmware(blob); diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 345587b..72c585c 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -220,7 +220,7 @@ void qe_assign_page(uint snum, uint para_ram_base) from CLKn pin, we have te change the function. */
-#define BRG_CLK (gd->brg_clk) +#define BRG_CLK (gd->arch.brg_clk)
int qe_set_brg(uint brg, uint rate) {