Hello Stefan,
In addition to Wolfgangs comment (patch is line wrapped): I just
checked the
440EP and the 440EPx users manual, and it seems that the original bit
masks
are correct. Which PPC4xx variant are you using? Please double check
again if
you your patch is correct.
I am working on another platform based on the PPC405GPr. You are correct in your observation and my patch is incorrect. The original bit masks are correct for the PPC440EP and PPC440EPx but **not** for the PPC405GPr so a correction is required.
According to the AMCC documentation, the EMPL, EMPH bit positions are as you defined them for the PPC440 processors and they are as I define them for the PPC405 processors (in the group of processors defined as CONFIG_EBC_PPC4xx_IBM_VER1). The PPC405EP is an exception since it does not seem to allow external bus mastering and these bits are reserved. Therefore a proper patch needs to set the bit position of the EMPL and EMPH fields differently with the CONFIG_EBC_PPC4xx_IBM_VER1 group accordingly. I can attempt a patch for that if you like.
My apologies for the line wrapping mistake (I believe my email client is not line wrapping but it got line wrapped somewhere else... possibly in the Microsoft exchange server).
Regards, Eugene