[U-Boot] [PATCH 09/10] MIPS: mips32/cache.S: store cache line size in t8 register

Synchronize the code with mips64/cache.S, in order to allow further unifications.

Signed-off-by: Gabor Juhos juhosg@openwrt.org Cc: Daniel Schwierzeck daniel.schwierzeck@googlemail.com --- arch/mips/cpu/mips32/cache.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 6d31909..e871d13 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -144,7 +144,7 @@ NESTED(mips_cache_reset, 0, ra) move RA, ra li t2, CONFIG_SYS_ICACHE_SIZE li t3, CONFIG_SYS_DCACHE_SIZE - li t4, CONFIG_SYS_CACHELINE_SIZE + li t8, CONFIG_SYS_CACHELINE_SIZE

li v0, MIPS_MAX_CACHE_SIZE

@@ -171,7 +171,7 @@ NESTED(mips_cache_reset, 0, ra) * Initialize the I-cache first, */ move a1, t2 - move a2, t4 + move a2, t8 PTR_LA t7, mips_init_icache jalr t7

@@ -179,7 +179,7 @@ NESTED(mips_cache_reset, 0, ra) * then initialize D-cache. */ move a1, t3 - move a2, t4 + move a2, t8 PTR_LA t7, mips_init_dcache jalr t7