Re: [U-Boot] [PATCH 2/2] xilinx_xiic: Fix transfer initialisation

On 6/25/19 2:33 PM, Marek Vasut wrote:

...

• ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,

• 	     XIIC_SR_BUS_BUSY_MASK, false, 3000, true);
  

Why 3 seconds wait ?

Right, seems kernel driver uses as small as 3ms timeout here. I'll change to that and verify.

thanks,

Tomas