On 06/03/2014 10:04 AM, Simon Glass wrote:
+Stephen
I don't think there's anything actionable for me in this email, although I guess I'll chime in on a couple of points:
I agree that the current way U-Boot parses DT is completely inadequate. The only way to parse it is to take a top-down recursive approach, with each node's driver initiating the parsing of any relevant child nodes. In other words, exactly how Linux (and likely *BSD, Solaris, ...) do it.
I really don't understand the hang up with GPIOs. Here are the possible HW situations as I see them:
1)
A single GPIO controller HW module, represented as a single DT node.
This should be: One node in DT. One DM device. One bind call (assuming that's the equivalent of Linux's probe()).
2)
A set of completely separate HW modules, each handling N GPIOs.
This should be: N nodes in DT. N DM devices. N bind calls.
3)
A single HW module that's represented in DT as a top-level node for the HW module and arbitrarily has N child nodes for some arbitrary bank concept within the HW module:
This should be: 1 (top-level) node in DT, N child nodes in DT, 1 or N DM devices, 1 bind call (for just the top-level node). The bind call can choose whether it creates 1 single DM device object for the top-level node, or 1 for each of the child node that it manually parses without additional bind calls. That's an implementation detail in the driver.
Note that Tegra should fall into case (1) above. I'm not familiar enough with Exynos HW (which was mentioned in the email I'm replying to but didn't bother quoting) to have an opinion re: which approach is most suitable for it.