On PPv2.2 we enable PHY polling, so we also need to configure the PHY address in the specific PHY address rgisters.
Signed-off-by: Stefan Roese sr@denx.de Cc: Stefan Chulski stefanc@marvell.com Cc: Kostya Porotchkin kostap@marvell.com Cc: Nadav Haklai nadavh@marvell.com ---
drivers/net/mvpp2.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 6537ee3f92..b506483aa9 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -499,9 +499,12 @@ do { \ #define SD1_CONTROL_XAUI_EN_MASK (0x1 << \ SD1_CONTROL_XAUI_EN_OFFS)
-#define MVPP22_SMI_MISC_CFG_REG 0x1204 +#define MVPP22_SMI_MISC_CFG_REG (MVPP22_SMI + 0x04) #define MVPP22_SMI_POLLING_EN BIT(10)
+#define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \ + (0x4 * (port))) + #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
/* Descriptor ring Macros */ @@ -5532,6 +5535,14 @@ static void mvpp2_stop(struct udevice *dev) mvpp2_cleanup_txqs(port); }
+static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port) +{ + writel(port->phyaddr, port->priv->iface_base + + MVPP22_SMI_PHY_ADDR_REG(port->gop_id)); + + return 0; +} + static int mvpp2_base_probe(struct udevice *dev) { struct mvpp2 *priv = dev_get_priv(dev); @@ -5670,6 +5681,9 @@ static int mvpp2_probe(struct udevice *dev) port->base = priv->iface_base + MVPP22_PORT_BASE + port->gop_id * MVPP22_PORT_OFFSET;
+ /* Set phy address of the port */ + mvpp22_smi_phy_addr_cfg(port); + /* GoP Init */ gop_port_init(port); }