Since 440EPx/GRx has problems with accessing the last 256 bytes of SDRAM via the Denali DDR/DDR2 controller, we set CONFIG_PRAM to 1 and reserve 1kByte of protected RAM. This way this memory will not get "touched" by U-Boot. And by passing "mem=${mem}" to the Linux kernel, Linux will not use this area either.
This patch adds this workaround for the following 440EPx boards: sequoia, lwmon5. Others should probably follow this example.
Here the description from the AMCC documentation:
CHIP_11: End of memory range area restricted access. Category: 3
Overview: The 440EPx DDR controller does not acknowledge any transaction which is determined to be crossing over the end-of-memory-range boundary, even if the starting address is within valid memory space. Any such transaction from any PLB4 master will result in a PLB time-out on PLB4 bus.
Impact: In case of such misaligned bursts, PLB4 masters will not retrieve any data at all, just the available data up to the end of memory, especially the 440 CPU. For example, if a CPU instruction required an operand located in memory within the last 7 words of memory, the DCU master would burst read 8 words to update the data cache and cross over the end-of-memory-range boundary. Such a DCU read would not be answered by the DDR controller, resulting in a PLB4 time-out and ultimately in a Machine Check interrupt. The data would be inaccessible to the CPU.
Workaround: Forbid any application to access the last 256 bytes of DDR memory. For example, make your operating system believe that the last 256 bytes of DDR memory are absent. AMCC has a patch that does this, available for Linux.
Signed-off-by: Stefan Roese sr@denx.de --- include/configs/lwmon5.h | 7 +++++-- include/configs/sequoia.h | 2 ++ 2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index c3f10c7..62c0e58 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * This program is free software; you can redistribute it and/or @@ -145,6 +145,8 @@ #else #define CFG_POST_ECC_ON 0 #endif +#define CONFIG_PRAM 1 /* don't use last 256 bytes */ + /* 440EPx errata CHIP 11 */
/* POST support */ #define CONFIG_POST (CFG_POST_CACHE | \ @@ -205,7 +207,8 @@ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ - "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\ + "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51" \ + " mem=${mem}\0" \ "flash_nfs=run nfsargs addip addtty addmisc;" \ "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty addmisc;" \ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index dfa8779..541f8bc 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -221,6 +221,8 @@ #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ #endif +#define CONFIG_PRAM 1 /* don't use last 256 bytes */ + /* 440EPx errata CHIP 11 */
/* * I2C