Fix the macro to set the pplmsb field (bit 3) of the RASTER_TIMING_0 register. It is used in order to support up to 2048 pixels per line.
Signed-off-by: Dario Binacchi dariobin@libero.it ---
Changes in v2: None
drivers/video/am335x-fb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c index 30543a945b..eb5add2a20 100644 --- a/drivers/video/am335x-fb.c +++ b/drivers/video/am335x-fb.c @@ -43,7 +43,7 @@ #define LCDC_DMA_CTRL_BURST_16 0x4 #define LCDC_DMA_CTRL_FIFO_TH(x) (((x) & GENMASK(2, 0)) << 8) /* LCD Timing_0 Register */ -#define LCDC_RASTER_TIMING_0_HORMSB(x) (((((x) >> 4) - 1) & 0x40) >> 4) +#define LCDC_RASTER_TIMING_0_HORMSB(x) ((((x) - 1) & BIT(10)) >> 7) #define LCDC_RASTER_TIMING_0_HORLSB(x) (((((x) >> 4) - 1) & GENMASK(5, 0)) << 4) #define LCDC_RASTER_TIMING_0_HSWLSB(x) ((((x) - 1) & GENMASK(5, 0)) << 10) #define LCDC_RASTER_TIMING_0_HFPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 16)