On Wednesday, September 17, 2014 at 01:29:15 PM, Chin Liang See wrote: [...]
A quick test from my side and result as below:
- SDRAM access is working where I can read and write to few spots. :)
SOCFPGA_CYCLONE5 # md 0 00000000: 00000000 aaaaaaaa aaaaaaaa aaaaaaaa ................ SOCFPGA_CYCLONE5 # mw 0 12345678 100 SOCFPGA_CYCLONE5 # md 0 00000000: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4. SOCFPGA_CYCLONE5 # md 100000 00100000: eafffffd fbff4b3f fffffffe fdff33be ....?K.......3.. SOCFPGA_CYCLONE5 # mw 100000 23456789 100 SOCFPGA_CYCLONE5 # md 100000 00100000: 23456789 23456789 23456789 23456789 .gE#.gE#.gE#.gE# SOCFPGA_CYCLONE5 #
What does that mean?
- Ethernet seems not working for me.
But I will look into this to find out any missing pieces.
SOCFPGA_CYCLONE5 # setenv ethaddr 02:11:22:33:44:55 SOCFPGA_CYCLONE5 # dhcp Speed: 1000, full duplex BOOTP broadcast 1 BOOTP broadcast 2 BOOTP broadcast 3 BOOTP broadcast 4 BOOTP broadcast 5 BOOTP broadcast 6 BOOTP broadcast 7 BOOTP broadcast 8 BOOTP broadcast 9 BOOTP broadcast 10 BOOTP broadcast 11 BOOTP broadcast 12 BOOTP broadcast 13 BOOTP broadcast 14 BOOTP broadcast 15 BOOTP broadcast 16 BOOTP broadcast 17
Retry time exceeded; starting again
This is on the SoCDK, right ?
- MMC is not enabled in SocFPGA.
I recall there is a patch from Pavel. I believe its pending for v2 due to some comments.
This should be in the tree in fact. Is CONFIG_CMD_MMC defined ?