28 Mar
2022
28 Mar
'22
2:43 p.m.
Hi Johan,
On 2022/3/4 07:52, Johan Jonker wrote:
Sync rk322x.dtsi from Linux version 5.17.
Signed-off-by: Johan Jonker jbx6244@gmail.com
Changed V2: update rename usb20_otg label
arch/arm/dts/rk3229-evb.dts | 2 +- arch/arm/dts/rk322x.dtsi | 846 +++++++++++++++++++++++++++++------- 2 files changed, 695 insertions(+), 153 deletions(-)
diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts index 66a3ba23..d2681d1a 100644 --- a/arch/arm/dts/rk3229-evb.dts +++ b/arch/arm/dts/rk3229-evb.dts @@ -69,6 +69,6 @@ status = "okay"; };
-&usb20_otg { +&usb_otg { status = "okay"; }; diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi index 3245da3c..8eed9e3a 100644 --- a/arch/arm/dts/rk322x.dtsi +++ b/arch/arm/dts/rk322x.dtsi @@ -1,7 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*
- Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
- */
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -9,6 +6,7 @@ #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rk3228-cru.h> #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/power/rk3228-power.h>
/ { #address-cells = <1>; @@ -20,8 +18,7 @@ serial0 = &uart0; serial1 = &uart1; serial2 = &uart2;
mmc0 = &emmc;mmc1 = &sdmmc;
I think this part will need to move to -u-boot.dtsi for U-Boot will use this to decide the boot order,
and U-Boot use emmc as mmc0 and sdmmc as mmc1 before kernel decide to add alias for mmc module.
Thanks,
- Kever
spi0 = &spi0;};
cpus {
@@ -33,13 +30,11 @@ compatible = "arm,cortex-a7"; reg = <0xf00>; resets = <&cru SRST_CORE0>;
operating-points = </* KHz uV */816000 1000000>;
operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ clock-latency = <40000>; clocks = <&cru ARMCLK>;enable-method = "psci";};
cpu1: cpu@f01 {
@@ -47,6 +42,9 @@ compatible = "arm,cortex-a7"; reg = <0xf01>; resets = <&cru SRST_CORE1>;
operating-points-v2 = <&cpu0_opp_table>;#cooling-cells = <2>; /* min followed by max */enable-method = "psci";};
cpu2: cpu@f02 {
@@ -54,6 +52,9 @@ compatible = "arm,cortex-a7"; reg = <0xf02>; resets = <&cru SRST_CORE2>;
operating-points-v2 = <&cpu0_opp_table>;#cooling-cells = <2>; /* min followed by max */enable-method = "psci";};
cpu3: cpu@f03 {
@@ -61,23 +62,37 @@ compatible = "arm,cortex-a7"; reg = <0xf03>; resets = <&cru SRST_CORE3>;
operating-points-v2 = <&cpu0_opp_table>;#cooling-cells = <2>; /* min followed by max */enable-method = "psci";
- amba {
compatible = "simple-bus";#address-cells = <1>;#size-cells = <1>;ranges;
- cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";opp-shared;
pdma: pdma@110f0000 {compatible = "arm,pl330", "arm,primecell";reg = <0x110f0000 0x4000>;interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;#dma-cells = <1>;clocks = <&cru ACLK_DMAC>;clock-names = "apb_pclk";
opp-408000000 {opp-hz = /bits/ 64 <408000000>;opp-microvolt = <950000>;clock-latency-ns = <40000>;opp-suspend;};opp-600000000 {opp-hz = /bits/ 64 <600000000>;opp-microvolt = <975000>;};opp-816000000 {opp-hz = /bits/ 64 <816000000>;opp-microvolt = <1000000>;};opp-1008000000 {opp-hz = /bits/ 64 <1008000000>;opp-microvolt = <1175000>;};opp-1200000000 {opp-hz = /bits/ 64 <1200000000>;opp-microvolt = <1275000>;@@ -90,6 +105,11 @@ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; };
- psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";method = "smc";- };
- timer { compatible = "arm,armv7-timer"; arm,cpu-registers-not-fw-configured;
@@ -107,12 +127,15 @@ #clock-cells = <0>; };
- display_subsystem: display-subsystem {
compatible = "rockchip,display-subsystem";ports = <&vop_out>;- };
- i2s1: i2s1@100b0000 { compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; reg = <0x100b0000 0x4000>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;#size-cells = <0>;@@ -126,8 +149,6 @@ compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; reg = <0x100c0000 0x4000>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;#size-cells = <0>;@@ -135,12 +156,23 @@ status = "disabled"; };
- spdif: spdif@100d0000 {
compatible = "rockchip,rk3228-spdif";reg = <0x100d0000 0x1000>;interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;clock-names = "mclk", "hclk";dmas = <&pdma 10>;dma-names = "tx";pinctrl-names = "default";pinctrl-0 = <&spdif_tx>;status = "disabled";- };
- i2s2: i2s2@100e0000 { compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; reg = <0x100e0000 0x4000>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;#size-cells = <0>;@@ -149,8 +181,124 @@ };
grf: syscon@11000000 {
compatible = "rockchip,rk3228-grf", "syscon";
compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";reg = <0x11000000 0x1000>;
#address-cells = <1>;#size-cells = <1>;io_domains: io-domains {compatible = "rockchip,rk3228-io-voltage-domain";status = "disabled";};power: power-controller {compatible = "rockchip,rk3228-power-controller";#power-domain-cells = <1>;#address-cells = <1>;#size-cells = <0>;power-domain@RK3228_PD_VIO {reg = <RK3228_PD_VIO>;clocks = <&cru ACLK_HDCP>,<&cru SCLK_HDCP>,<&cru ACLK_IEP>,<&cru HCLK_IEP>,<&cru ACLK_RGA>,<&cru HCLK_RGA>,<&cru SCLK_RGA>;pm_qos = <&qos_hdcp>,<&qos_iep>,<&qos_rga_r>,<&qos_rga_w>;#power-domain-cells = <0>;};power-domain@RK3228_PD_VOP {reg = <RK3228_PD_VOP>;clocks =<&cru ACLK_VOP>,<&cru DCLK_VOP>,<&cru HCLK_VOP>;pm_qos = <&qos_vop>;#power-domain-cells = <0>;};power-domain@RK3228_PD_VPU {reg = <RK3228_PD_VPU>;clocks = <&cru ACLK_VPU>,<&cru HCLK_VPU>;pm_qos = <&qos_vpu>;#power-domain-cells = <0>;};power-domain@RK3228_PD_RKVDEC {reg = <RK3228_PD_RKVDEC>;clocks = <&cru ACLK_RKVDEC>,<&cru HCLK_RKVDEC>,<&cru SCLK_VDEC_CABAC>,<&cru SCLK_VDEC_CORE>;pm_qos = <&qos_rkvdec_r>,<&qos_rkvdec_w>;#power-domain-cells = <0>;};power-domain@RK3228_PD_GPU {reg = <RK3228_PD_GPU>;clocks = <&cru ACLK_GPU>;pm_qos = <&qos_gpu>;#power-domain-cells = <0>;};};u2phy0: usb2phy@760 {compatible = "rockchip,rk3228-usb2phy";reg = <0x0760 0x0c>;clocks = <&cru SCLK_OTGPHY0>;clock-names = "phyclk";clock-output-names = "usb480m_phy0";#clock-cells = <0>;status = "disabled";u2phy0_otg: otg-port {interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "otg-bvalid", "otg-id","linestate";#phy-cells = <0>;status = "disabled";};u2phy0_host: host-port {interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "linestate";#phy-cells = <0>;status = "disabled";};};u2phy1: usb2phy@800 {compatible = "rockchip,rk3228-usb2phy";reg = <0x0800 0x0c>;clocks = <&cru SCLK_OTGPHY1>;clock-names = "phyclk";clock-output-names = "usb480m_phy1";#clock-cells = <0>;status = "disabled";u2phy1_otg: otg-port {interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "linestate";#phy-cells = <0>;status = "disabled";};u2phy1_host: host-port {interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "linestate";#phy-cells = <0>;status = "disabled";};};};
uart0: serial@11010000 {
@@ -189,12 +337,29 @@ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; pinctrl-names = "default";
pinctrl-0 = <&uart21_xfer>;
pinctrl-0 = <&uart2_xfer>;reg-shift = <2>; reg-io-width = <4>; status = "disabled"; };
efuse: efuse@11040000 {
compatible = "rockchip,rk3228-efuse";reg = <0x11040000 0x20>;clocks = <&cru PCLK_EFUSE_256>;clock-names = "pclk_efuse";#address-cells = <1>;#size-cells = <1>;/* Data cells */efuse_id: id@7 {reg = <0x7 0x10>;};cpu_leakage: cpu_leakage@17 {reg = <0x17 0x1>;};};
i2c0: i2c@11050000 { compatible = "rockchip,rk3228-i2c"; reg = <0x11050000 0x1000>;
@@ -247,12 +412,32 @@ status = "disabled"; };
- spi0: spi@11090000 {
compatible = "rockchip,rk3228-spi";reg = <0x11090000 0x1000>;interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;#address-cells = <1>;#size-cells = <0>;clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;clock-names = "spiclk", "apb_pclk";pinctrl-names = "default";pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;status = "disabled";- };
- wdt: watchdog@110a0000 {
compatible = "rockchip,rk3228-wdt", "snps,dw-wdt";reg = <0x110a0000 0x100>;interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru PCLK_CPU>;status = "disabled";- };
- pwm0: pwm@110b0000 { compatible = "rockchip,rk3288-pwm"; reg = <0x110b0000 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>;
clock-names = "pwm";@@ -263,7 +448,6 @@ reg = <0x110b0010 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>;
clock-names = "pwm";@@ -274,7 +458,6 @@ reg = <0x110b0020 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>;
clock-names = "pwm";@@ -285,18 +468,17 @@ reg = <0x110b0030 0x10>; #pwm-cells = <2>; clocks = <&cru PCLK_PWM>;
clock-names = "pwm";pinctrl-names = "default"; pinctrl-0 = <&pwm3_pin>; status = "disabled"; };
timer: timer@110c0000 {
compatible = "rockchip,rk3288-timer";
compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
clocks = <&xin24m>, <&cru PCLK_TIMER>;clock-names = "timer", "pclk";
clocks = <&cru PCLK_TIMER>, <&xin24m>;clock-names = "pclk", "timer";};
cru: clock-controller@110e0000 {
@@ -305,8 +487,29 @@ rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>;
assigned-clocks = <&cru PLL_GPLL>;assigned-clock-rates = <594000000>;
assigned-clocks =<&cru PLL_GPLL>, <&cru ARMCLK>,<&cru PLL_CPLL>, <&cru ACLK_PERI>,<&cru HCLK_PERI>, <&cru PCLK_PERI>,<&cru ACLK_CPU>, <&cru HCLK_CPU>,<&cru PCLK_CPU>;assigned-clock-rates =<594000000>, <816000000>,<500000000>, <150000000>,<150000000>, <75000000>,<150000000>, <150000000>,<75000000>;};
pdma: pdma@110f0000 {
compatible = "arm,pl330", "arm,primecell";reg = <0x110f0000 0x4000>;interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;#dma-cells = <1>;arm,pl330-periph-burst;clocks = <&cru ACLK_DMAC>;clock-names = "apb_pclk";};
thermal-zones {
@@ -338,12 +541,18 @@ map0 { trip = <&cpu_alert0>; cooling-device =
<&cpu0 THERMAL_NO_LIMIT 6>;
<&cpu0 THERMAL_NO_LIMIT 6>,<&cpu1 THERMAL_NO_LIMIT 6>,<&cpu2 THERMAL_NO_LIMIT 6>,<&cpu3 THERMAL_NO_LIMIT 6>; }; map1 { trip = <&cpu_alert1>; cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; };@@ -355,53 +564,220 @@ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; clock-names = "tsadc", "apb_pclk";
assigned-clocks = <&cru SCLK_TSADC>;assigned-clock-rates = <32768>;
pinctrl-0 = <&otp_gpio>;
pinctrl-0 = <&otp_pin>;
pinctrl-2 = <&otp_gpio>;#thermal-sensor-cells = <0>;
pinctrl-2 = <&otp_pin>;#thermal-sensor-cells = <1>;
- sdmmc: dwmmc@30000000 {
- hdmi_phy: hdmi-phy@12030000 {
compatible = "rockchip,rk3228-hdmi-phy";reg = <0x12030000 0x10000>;clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;clock-names = "sysclk", "refoclk", "refpclk";#clock-cells = <0>;clock-output-names = "hdmiphy_phy";#phy-cells = <0>;status = "disabled";- };
- gpu: gpu@20000000 {
compatible = "rockchip,rk3228-mali", "arm,mali-400";reg = <0x20000000 0x10000>;interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "gp","gpmmu","pp0","ppmmu0","pp1","ppmmu1";clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;clock-names = "bus", "core";power-domains = <&power RK3228_PD_GPU>;resets = <&cru SRST_GPU_A>;status = "disabled";- };
- vpu: video-codec@20020000 {
compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu";reg = <0x20020000 0x800>;interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "vepu", "vdpu";clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;clock-names = "aclk", "hclk";iommus = <&vpu_mmu>;power-domains = <&power RK3228_PD_VPU>;- };
- vpu_mmu: iommu@20020800 {
compatible = "rockchip,iommu";reg = <0x20020800 0x100>;interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;clock-names = "aclk", "iface";power-domains = <&power RK3228_PD_VPU>;#iommu-cells = <0>;- };
- vdec: video-codec@20030000 {
compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec";reg = <0x20030000 0x480>;interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;clock-names = "axi", "ahb", "cabac", "core";assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;assigned-clock-rates = <300000000>, <300000000>;iommus = <&vdec_mmu>;power-domains = <&power RK3228_PD_RKVDEC>;- };
- vdec_mmu: iommu@20030480 {
compatible = "rockchip,iommu";reg = <0x20030480 0x40>, <0x200304c0 0x40>;interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;clock-names = "aclk", "iface";power-domains = <&power RK3228_PD_RKVDEC>;#iommu-cells = <0>;- };
- vop: vop@20050000 {
compatible = "rockchip,rk3228-vop";reg = <0x20050000 0x1ffc>;interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;clock-names = "aclk_vop", "dclk_vop", "hclk_vop";resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;reset-names = "axi", "ahb", "dclk";iommus = <&vop_mmu>;power-domains = <&power RK3228_PD_VOP>;status = "disabled";vop_out: port {#address-cells = <1>;#size-cells = <0>;vop_out_hdmi: endpoint@0 {reg = <0>;remote-endpoint = <&hdmi_in_vop>;};};- };
- vop_mmu: iommu@20053f00 {
compatible = "rockchip,iommu";reg = <0x20053f00 0x100>;interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;clock-names = "aclk", "iface";power-domains = <&power RK3228_PD_VOP>;#iommu-cells = <0>;status = "disabled";- };
- rga: rga@20060000 {
compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";reg = <0x20060000 0x1000>;interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;clock-names = "aclk", "hclk", "sclk";power-domains = <&power RK3228_PD_VIO>;resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;reset-names = "core", "axi", "ahb";- };
- iep_mmu: iommu@20070800 {
compatible = "rockchip,iommu";reg = <0x20070800 0x100>;interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;clock-names = "aclk", "iface";power-domains = <&power RK3228_PD_VIO>;#iommu-cells = <0>;status = "disabled";- };
- hdmi: hdmi@200a0000 {
compatible = "rockchip,rk3228-dw-hdmi";reg = <0x200a0000 0x20000>;reg-io-width = <4>;interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;assigned-clocks = <&cru SCLK_HDMI_PHY>;assigned-clock-parents = <&hdmi_phy>;clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>;clock-names = "isfr", "iahb", "cec";pinctrl-names = "default";pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;resets = <&cru SRST_HDMI_P>;reset-names = "hdmi";phys = <&hdmi_phy>;phy-names = "hdmi";rockchip,grf = <&grf>;status = "disabled";ports {hdmi_in: port {#address-cells = <1>;#size-cells = <0>;hdmi_in_vop: endpoint@0 {reg = <0>;remote-endpoint = <&vop_out_hdmi>;};};};- };
- sdmmc: mmc@30000000 { compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x30000000 0x4000>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- sdio: dwmmc@30010000 {
- sdio: mmc@30010000 { compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x30010000 0x4000>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- emmc: dwmmc@30020000 {
compatible = "rockchip,rk3288-dw-mshc";
- emmc: mmc@30020000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";clock-frequency = <37500000>;max-frequency = <37500000>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
default-sample-phase = <158>;num-slots = <1>;
rockchip,default-sample-phase = <158>;@@ -410,13 +786,79 @@ status = "disabled"; };
- usb20_otg: usb@30040000 {
compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb",
- usb_otg: usb@30040000 {
compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", "snps,dwc2";
hnp-srp-disable;
clocks = <&cru HCLK_OTG>;clock-names = "otg";g-np-tx-fifo-size = <16>;g-rx-fifo-size = <280>;g-tx-fifo-size = <256 128 128 64 32 16>;phys = <&u2phy0_otg>;phy-names = "usb2-phy";status = "disabled";- };
- usb_host0_ehci: usb@30080000 {
compatible = "generic-ehci";reg = <0x30080000 0x20000>;interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru HCLK_HOST0>, <&u2phy0>;phys = <&u2phy0_host>;phy-names = "usb";status = "disabled";- };
- usb_host0_ohci: usb@300a0000 {
compatible = "generic-ohci";reg = <0x300a0000 0x20000>;interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru HCLK_HOST0>, <&u2phy0>;phys = <&u2phy0_host>;phy-names = "usb";status = "disabled";- };
- usb_host1_ehci: usb@300c0000 {
compatible = "generic-ehci";reg = <0x300c0000 0x20000>;interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru HCLK_HOST1>, <&u2phy1>;phys = <&u2phy1_otg>;phy-names = "usb";status = "disabled";- };
- usb_host1_ohci: usb@300e0000 {
compatible = "generic-ohci";reg = <0x300e0000 0x20000>;interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru HCLK_HOST1>, <&u2phy1>;phys = <&u2phy1_otg>;phy-names = "usb";status = "disabled";- };
- usb_host2_ehci: usb@30100000 {
compatible = "generic-ehci";reg = <0x30100000 0x20000>;interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru HCLK_HOST2>, <&u2phy1>;phys = <&u2phy1_host>;phy-names = "usb";status = "disabled";- };
- usb_host2_ohci: usb@30120000 {
compatible = "generic-ohci";reg = <0x30120000 0x20000>;interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru HCLK_HOST2>, <&u2phy1>;phys = <&u2phy1_host>;phy-names = "usb";@@ -439,6 +881,51 @@ status = "disabled"; };
- qos_iep: qos@31030080 {
compatible = "rockchip,rk3228-qos", "syscon";reg = <0x31030080 0x20>;- };
- qos_rga_w: qos@31030100 {
compatible = "rockchip,rk3228-qos", "syscon";reg = <0x31030100 0x20>;- };
- qos_hdcp: qos@31030180 {
compatible = "rockchip,rk3228-qos", "syscon";reg = <0x31030180 0x20>;- };
- qos_rga_r: qos@31030200 {
compatible = "rockchip,rk3228-qos", "syscon";reg = <0x31030200 0x20>;- };
- qos_vpu: qos@31040000 {
compatible = "rockchip,rk3228-qos", "syscon";reg = <0x31040000 0x20>;- };
- qos_gpu: qos@31050000 {
compatible = "rockchip,rk3228-qos", "syscon";reg = <0x31050000 0x20>;- };
- qos_vop: qos@31060000 {
compatible = "rockchip,rk3228-qos", "syscon";reg = <0x31060000 0x20>;- };
- qos_rkvdec_r: qos@31070000 {
compatible = "rockchip,rk3228-qos", "syscon";reg = <0x31070000 0x20>;- };
- qos_rkvdec_w: qos@31070080 {
compatible = "rockchip,rk3228-qos", "syscon";reg = <0x31070080 0x20>;- };
- gic: interrupt-controller@32010000 { compatible = "arm,gic-400"; interrupt-controller;
@@ -459,7 +946,7 @@ #size-cells = <1>; ranges;
gpio0: gpio0@11110000 {
gpio0: gpio@11110000 { compatible = "rockchip,gpio-bank"; reg = <0x11110000 0x100>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;@@ -472,7 +959,7 @@ #interrupt-cells = <2>; };
gpio1: gpio1@11120000 {
gpio1: gpio@11120000 { compatible = "rockchip,gpio-bank"; reg = <0x11120000 0x100>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;@@ -485,7 +972,7 @@ #interrupt-cells = <2>; };
gpio2: gpio2@11130000 {
gpio2: gpio@11130000 { compatible = "rockchip,gpio-bank"; reg = <0x11130000 0x100>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;@@ -498,7 +985,7 @@ #interrupt-cells = <2>; };
gpio3: gpio3@11140000 {
gpio3: gpio@11140000 { compatible = "rockchip,gpio-bank"; reg = <0x11140000 0x100>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;@@ -529,222 +1016,277 @@
sdmmc { sdmmc_clk: sdmmc-clk {
rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; }; sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; }; sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,<1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,<1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,<1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,<1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,<1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,<1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; };};
sdio { sdio_clk: sdio-clk {
rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; }; sdio_cmd: sdio-cmd {
rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; }; sdio_bus4: sdio-bus4 {
rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,<3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,<3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,<3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,<3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,<3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,<3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; };};
emmc { emmc_clk: emmc-clk {
rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; }; emmc_cmd: emmc-cmd {
rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>; }; emmc_bus8: emmc-bus8 {
rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>,<1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>,<1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,<1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,<1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>,<1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,<1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>,<1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,<1 RK_PD1 2 &pcfg_pull_none>,<1 RK_PD2 2 &pcfg_pull_none>,<1 RK_PD3 2 &pcfg_pull_none>,<1 RK_PD4 2 &pcfg_pull_none>,<1 RK_PD5 2 &pcfg_pull_none>,<1 RK_PD6 2 &pcfg_pull_none>,<1 RK_PD7 2 &pcfg_pull_none>; };};
gmac { rgmii_pins: rgmii-pins {
rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,<2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,<2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,<2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,<2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,<2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,<2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,<2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,<2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,<2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,<2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,<2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,<2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,<2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,<2 RK_PB4 1 &pcfg_pull_none>,<2 RK_PD1 1 &pcfg_pull_none>,<2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,<2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,<2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,<2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,<2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,<2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,<2 RK_PC1 1 &pcfg_pull_none>,<2 RK_PC0 1 &pcfg_pull_none>,<2 RK_PC5 2 &pcfg_pull_none>,<2 RK_PC4 2 &pcfg_pull_none>,<2 RK_PB3 1 &pcfg_pull_none>,<2 RK_PB0 1 &pcfg_pull_none>; }; rmii_pins: rmii-pins {
rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,<2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,<2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,<2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,<2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,<2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,<2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,<2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,<2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,<2 RK_PB4 1 &pcfg_pull_none>,<2 RK_PD1 1 &pcfg_pull_none>,<2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,<2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,<2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,<2 RK_PC1 1 &pcfg_pull_none>,<2 RK_PC0 1 &pcfg_pull_none>,<2 RK_PB0 1 &pcfg_pull_none>,<2 RK_PB7 1 &pcfg_pull_none>; }; phy_pins: phy-pins {
rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>,<2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,<2 RK_PB0 2 &pcfg_pull_none>;};};hdmi {hdmi_hpd: hdmi-hpd {rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;};hdmii2c_xfer: hdmii2c-xfer {rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,<0 RK_PA7 2 &pcfg_pull_none>;};hdmi_cec: hdmi-cec {rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; };};
i2c0 { i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,<0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,<0 RK_PA1 1 &pcfg_pull_none>; };};
i2c1 { i2c1_xfer: i2c1-xfer {
rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,<0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,<0 RK_PA3 1 &pcfg_pull_none>; };};
i2c2 { i2c2_xfer: i2c2-xfer {
rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,<2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,<2 RK_PC5 1 &pcfg_pull_none>; };};
i2c3 { i2c3_xfer: i2c3-xfer {
rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,<0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,<0 RK_PA7 1 &pcfg_pull_none>;};};spi0 {spi0_clk: spi0-clk {rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;};spi0_cs0: spi0-cs0 {rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;};spi0_tx: spi0-tx {rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;};spi0_rx: spi0-rx {rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;};spi0_cs1: spi0-cs1 {rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;};};spi1 {spi1_clk: spi1-clk {rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;};spi1_cs0: spi1-cs0 {rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;};spi1_rx: spi1-rx {rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;};spi1_tx: spi1-tx {rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;};spi1_cs1: spi1-cs1 {rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>; };};
i2s1 { i2s1_bus: i2s1-bus {
rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,<0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,<0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,<0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,<0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,<0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,<1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,<1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,<1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,<0 RK_PB1 1 &pcfg_pull_none>,<0 RK_PB3 1 &pcfg_pull_none>,<0 RK_PB4 1 &pcfg_pull_none>,<0 RK_PB5 1 &pcfg_pull_none>,<0 RK_PB6 1 &pcfg_pull_none>,<1 RK_PA2 2 &pcfg_pull_none>,<1 RK_PA4 2 &pcfg_pull_none>,<1 RK_PA5 2 &pcfg_pull_none>; };};
pwm0 { pwm0_pin: pwm0-pin {
rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; };};
pwm1 { pwm1_pin: pwm1-pin {
rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; };};
pwm2 { pwm2_pin: pwm2-pin {
rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; };};
pwm3 { pwm3_pin: pwm3-pin {
rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;};};spdif {spdif_tx: spdif-tx {rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>; };};
tsadc {
otp_gpio: otp-gpio {
otp_pin: otp-pin { rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; otp_out: otp-out {
rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; };};
uart0 { uart0_xfer: uart0-xfer {
rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>,<2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,<2 RK_PD3 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts {
rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>; }; uart0_rts: uart0-rts {
rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>; };};
uart1 { uart1_xfer: uart1-xfer {
rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,<1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,<1 RK_PB2 1 &pcfg_pull_none>; }; uart1_cts: uart1-cts {
rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>; }; uart1_rts: uart1-rts {
rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; };};
uart2 { uart2_xfer: uart2-xfer {
rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>,<1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,<1 RK_PC3 2 &pcfg_pull_none>; };
uart2_cts: uart2-cts {rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
uart21_xfer: uart21-xfer {rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,<1 RK_PB1 2 &pcfg_pull_none>; };
uart2_rts: uart2-rts {rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
uart2_cts: uart2-cts {rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; };
};uart2-1 {uart21_xfer: uart21-xfer {rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,<1 9 RK_FUNC_2 &pcfg_pull_none>;
uart2_rts: uart2-rts {rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; };