i.CoreM6 1.5 is an another i.CoreM6 QDL cpu modules which can be connected to EDIMM starter kit design with eMMC and MIPI-CSI interfaces suitable for Android and video capture application.
notable features: CPU NXP i.MX6 S/DL/D/Q, Up to 4 x Cortex-A9@800MHz Memory Up to 2 GB DDR3-1066 Video Interfaces Up to 1 Parallel Up to 2 LVDS HDMI 1.4 port 8 bit CSI INPUT MIPI-CSI INPUT 1 x 10/100 Ethernet interface, 2 x USB, 1 x PCIe, 1 x I2S etc
This patch adds support for Quad/Dual and DualLite/Solo SOM's on MIPI starter kit with boot from SD and eMMC.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/dts/Makefile | 2 ++ arch/arm/dts/imx6dl-icore-mipi.dts | 21 ++++++++++++++++ arch/arm/dts/imx6q-icore-mipi.dts | 21 ++++++++++++++++ arch/arm/dts/imx6qdl-icore.dtsi | 28 +++++++++++++++++++++ board/engicam/common/board.c | 5 ++++ configs/imx6qdl_icore_mipi_defconfig | 49 ++++++++++++++++++++++++++++++++++++ 6 files changed, 126 insertions(+) create mode 100644 arch/arm/dts/imx6dl-icore-mipi.dts create mode 100644 arch/arm/dts/imx6q-icore-mipi.dts create mode 100644 configs/imx6qdl_icore_mipi_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a895c70..8515645 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -374,9 +374,11 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ imx6sl-evk.dtb \ imx6sll-evk.dtb \ imx6dl-icore.dtb \ + imx6dl-icore-mipi.dtb \ imx6dl-icore-rqs.dtb \ imx6q-cm-fx6.dtb \ imx6q-icore.dtb \ + imx6q-icore-mipi.dtb \ imx6q-icore-rqs.dtb \ imx6q-logicpd.dtb \ imx6sx-sabreauto.dtb \ diff --git a/arch/arm/dts/imx6dl-icore-mipi.dts b/arch/arm/dts/imx6dl-icore-mipi.dts new file mode 100644 index 0000000..3a444c0 --- /dev/null +++ b/arch/arm/dts/imx6dl-icore-mipi.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2017 Engicam S.r.l. + * Copyright (C) 2017 Amarula Solutions B.V. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-icore.dtsi" + +/ { + model = "Engicam i.CoreM6 DualLite/Solo MIPI Starter Kit"; + compatible = "engicam,imx6-icore", "fsl,imx6dl"; +}; + +&usdhc3 { + u-boot,dm-spl; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6q-icore-mipi.dts b/arch/arm/dts/imx6q-icore-mipi.dts new file mode 100644 index 0000000..527f52c --- /dev/null +++ b/arch/arm/dts/imx6q-icore-mipi.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2017 Engicam S.r.l. + * Copyright (C) 2017 Amarula Solutions B.V. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-icore.dtsi" + +/ { + model = "Engicam i.CoreM6 Quad/Dual MIPI Starter Kit"; + compatible = "engicam,imx6-icore", "fsl,imx6q"; +}; + +&usdhc3 { + u-boot,dm-spl; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6qdl-icore.dtsi b/arch/arm/dts/imx6qdl-icore.dtsi index 06d9bc3..913dc99 100644 --- a/arch/arm/dts/imx6qdl-icore.dtsi +++ b/arch/arm/dts/imx6qdl-icore.dtsi @@ -44,6 +44,10 @@ #include <dt-bindings/input/input.h>
/ { + aliases { + mmc1 = &usdhc3; + }; + memory { reg = <0x10000000 0x80000000>; }; @@ -126,6 +130,14 @@ status = "okay"; };
+&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + no-1-8-v; + non-removable; + status = "disabled"; +}; + &iomuxc { pinctrl_enet: enetgrp { fsl,pins = < @@ -219,4 +231,20 @@ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070 >; }; + + pinctrl_usdhc3: usdhc3grp { + u-boot,dm-spl; + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; }; diff --git a/board/engicam/common/board.c b/board/engicam/common/board.c index f633c71..0160418 100644 --- a/board/engicam/common/board.c +++ b/board/engicam/common/board.c @@ -41,6 +41,11 @@ static void setenv_fdt_file(void) env_set("fdt_file", "imx6q-icore.dtb"); else if(is_mx6dl() || is_mx6solo()) env_set("fdt_file", "imx6dl-icore.dtb"); + } else if (!strcmp(cmp_dtb, "imx6q-icore-mipi")) { + if (is_mx6dq()) + env_set("fdt_file", "imx6q-icore-mipi.dtb"); + else if(is_mx6dl() || is_mx6solo()) + env_set("fdt_file", "imx6dl-icore-mipi.dtb"); } else if (!strcmp(cmp_dtb, "imx6q-icore-rqs")) { if (is_mx6dq()) env_set("fdt_file", "imx6q-icore-rqs.dtb"); diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig new file mode 100644 index 0000000..3bec7e2 --- /dev/null +++ b/configs/imx6qdl_icore_mipi_defconfig @@ -0,0 +1,49 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_MX6Q_ENGICAM=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +# CONFIG_CMD_BMODE is not set +CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-mipi" +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_SPL=y +CONFIG_SPL_EXT_SUPPORT=y +CONFIG_SPL_OS_BOOT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="icorem6qdl-mipi> " +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_LIST="imx6q-icore-mipi imx6dl-icore-mipi" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_I2C_MXC=y +CONFIG_PHYLIB=y +CONFIG_PHY_SMSC=y +CONFIG_FEC_MXC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DEBUG_UART_MXC=y +CONFIG_DEBUG_UART_BASE=0x021f0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y