The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It does not directly affect the data cache and particular cannot be used to flush or invalidate it. RISC-V does not have instructions for explicit cache control. Remove the flush_dcache_all implementation and its use in all dcache-specific functions in lib/cache.c.
This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c.
Signed-off-by: Lukas Auer lukas.auer@aisec.fraunhofer.de --- This patch only removes the implementation itself and its use in dcache-specific functions in lib/cache.c. There are more uses of it in arch/riscv/, which this patch does not remove.
arch/riscv/lib/cache.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index ae5c60716f..203e287612 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -13,11 +13,10 @@ void invalidate_icache_all(void)
void flush_dcache_all(void) { - asm volatile ("fence" :::"memory"); } + void flush_dcache_range(unsigned long start, unsigned long end) { - flush_dcache_all(); }
void invalidate_icache_range(unsigned long start, unsigned long end) @@ -31,7 +30,6 @@ void invalidate_icache_range(unsigned long start, unsigned long end)
void invalidate_dcache_range(unsigned long start, unsigned long end) { - flush_dcache_all(); }
void cache_flush(void)