BSP boot0 executes resistor calibration before clocks are initialized. Let's do that.
Signed-off-by: Jernej Skrabec jernej.skrabec@gmail.com --- arch/arm/mach-sunxi/clock_sun50i_h6.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index e5846e6381ff..32119ad16555 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -12,9 +12,14 @@ void clock_init_safe(void) struct sunxi_prcm_reg *const prcm = (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
- /* this seems to enable PLLs on H616 */ - if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) { + /* this seems to enable PLLs on H616 */ setbits_le32(&prcm->sys_pwroff_gating, 0x10); + setbits_le32(&prcm->res_cal_ctrl, 2); + } + + clrbits_le32(&prcm->res_cal_ctrl, 1); + setbits_le32(&prcm->res_cal_ctrl, 1);
clock_set_pll1(408000000);