Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties for Rockchip RK3588 SoC to boot the SPL.
Signed-off-by: Jagan Teki jagan@edgeble.ai --- arch/arm/dts/rk3588-u-boot.dtsi | 7 +++++ arch/arm/dts/rk3588s-u-boot.dtsi | 45 ++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) create mode 100644 arch/arm/dts/rk3588-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588s-u-boot.dtsi
diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi new file mode 100644 index 0000000000..4c8ac804d6 --- /dev/null +++ b/arch/arm/dts/rk3588-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include "rockchip-u-boot.dtsi" +#include "rk3588s-u-boot.dtsi" diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi new file mode 100644 index 0000000000..cfcbef2fc2 --- /dev/null +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include "rockchip-u-boot.dtsi" + +/ { + dmc { + compatible = "rockchip,rk3588-dmc"; + u-boot,dm-pre-reloc; + status = "okay"; + }; + + pmu1_grf: syscon@fd58a000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3588-pmu1-grf", "syscon"; + reg = <0x0 0xfd58a000 0x0 0x2000>; + }; +}; + +&xin24m { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&cru { + u-boot,dm-spl; + status = "okay"; +}; + +&sys_grf { + u-boot,dm-spl; + status = "okay"; +}; + +&uart2 { + clock-frequency = <24000000>; + u-boot,dm-spl; + status = "okay"; +}; + +&ioc { + u-boot,dm-spl; +};