
24 Oct
2018
24 Oct
'18
4:19 p.m.
Hi Bin,
On Mon, 2018-10-22 at 14:23 +0800, Bin Meng wrote:
Hi Lukas,
On Sat, Oct 20, 2018 at 6:09 AM Lukas Auer lukas.auer@aisec.fraunhofer.de wrote:
RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_64I to match
ARCH_RV64I
Fixed in v2.
Thanks, Lukas
this convention.
Signed-off-by: Lukas Auer lukas.auer@aisec.fraunhofer.de
arch/riscv/Kconfig | 16 ++++++++-------- arch/riscv/lib/setjmp.S | 2 +- configs/ax25-ae350_defconfig | 2 +- configs/qemu-riscv64_defconfig | 2 +- include/config_distro_bootcmd.h | 8 ++++---- 5 files changed, 15 insertions(+), 15 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
Regards, Bin