On Mon, Feb 03, 2020 at 09:47:04AM +0100, Marek Vasut wrote:
On 2/3/20 9:24 AM, Marek Vasut wrote:
On 2/2/20 9:26 PM, Tom Rini wrote:
On Sun, Feb 02, 2020 at 06:18:53PM +0100, Marek Vasut wrote:
The following changes since commit 80e99adbe47d1c8590f9b971ac52257fdc51a5ec:
Merge tag 'uniphier-v2020.04-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier (2020-01-31 13:26:28 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to 56c24875d92adcf214d97f5798e11c1b7b5e27fa:
ddr: altera: Add DDR2 support to Gen5 driver (2020-02-02 18:18:05 +0100)
A see a ton of failures: aarch64: + socfpga_agilex
OK, this one I see, let's add this patch
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index da81137e84..87c73457a0 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -150,10 +150,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /*
- L4 Watchdog
*/ -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_WATCHDOG -#define CONFIG_HW_WATCHDOG -#else +#ifndef CONFIG_SPL_BUILD #undef CONFIG_HW_WATCHDOG #undef CONFIG_DESIGNWARE_WATCHDOG #endif
To be clear, I'm expecting a new PR, thanks.