On Tue, Jan 19, 2016 at 11:27 AM, Bin Meng bmeng.cn@gmail.com wrote:
On Tue, Jan 19, 2016 at 11:19 AM, Simon Glass sjg@chromium.org wrote:
At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API.
In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need.
While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device.
Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected.
This patch includes Bin's fix-up patch from here:
https://patchwork.ozlabs.org/patch/569478/
Signed-off-by: Simon Glass sjg@chromium.org Signed-off-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Bin Meng bmeng.cn@gmail.com
Changes in v5:
- Squash in Bin's fix-up patch
Changes in v4:
- Add BIOS_CTRL address for PCH9
Changes in v3:
- Use the set_spi_protect() PCH method
Changes in v2:
- Adjust code for earlier commits
- Move the SPI base code into the PCH drivers
arch/x86/cpu/coreboot/pci.c | 3 +- arch/x86/cpu/irq.c | 7 +- arch/x86/cpu/ivybridge/bd82x6x.c | 47 ++++++++++- arch/x86/dts/bayleybay.dts | 160 +++++++++++++++++++----------------- arch/x86/dts/broadwell_som-6896.dts | 24 ++++-- arch/x86/dts/chromebook_link.dts | 5 +- arch/x86/dts/chromebox_panther.dts | 34 ++++---- arch/x86/dts/crownbay.dts | 150 +++++++++++++++++---------------- arch/x86/dts/galileo.dts | 99 +++++++++++----------- arch/x86/dts/minnowmax.dts | 158 ++++++++++++++++++----------------- arch/x86/dts/qemu-x86_i440fx.dts | 26 +++--- arch/x86/dts/qemu-x86_q35.dts | 38 +++++---- drivers/spi/ich.c | 152 ++++++++-------------------------- 13 files changed, 461 insertions(+), 442 deletions(-)
Tested-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86/master, thanks!