On Friday 24 September 2021 16:18:46 Stefan Roese wrote:
On 24.09.21 16:11, Pali Rohár wrote:
Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe Root Complex mode.
Same change was included in TF-A project: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9408
Signed-off-by: Pali Rohár pali@kernel.org
Did you experience some problems without this change?
I think I did not see problems neither with nor without this change.
Code just aligns with what is written in documentation guidelines.
If yes, which?
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
drivers/phy/marvell/comphy_a3700.c | 2 +- drivers/phy/marvell/comphy_a3700.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 5eb137db4884..afa1295bbdb8 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -200,7 +200,7 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) * 6. Enable the output of 100M/125M/500M clock */ reg_set16(phy_addr(PCIE, MISC_REG0),
0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF);
0xA00D | rb_clk500m_en | rb_txdclk_2x_sel | rb_clk100m_125m_en, 0xFFFF);
- Enable TX
diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h index 8748c6c84ae6..23c8ffbff44d 100644 --- a/drivers/phy/marvell/comphy_a3700.h +++ b/drivers/phy/marvell/comphy_a3700.h @@ -120,6 +120,7 @@ static inline void __iomem *phy_addr(enum phy_unit unit, u32 addr) #define MISC_REG0 0x4f #define rb_clk100m_125m_en BIT(4) +#define rb_txdclk_2x_sel BIT(6) #define rb_clk500m_en BIT(7) #define rb_ref_clk_sel BIT(10)
Viele Grüße, Stefan
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