Re: [PATCH v4 2/3] arch/riscv: add semihosting support for RISC-V

On Mon, Sep 19, 2022 at 05:19:07PM +0530, Kautuk Consul wrote:

We add RISC-V semihosting based serial console for JTAG based early debugging.

The RISC-V semihosting specification is available at: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-...

Signed-off-by: Anup Patel apatel@ventanamicro.com Signed-off-by: Kautuk Consul kconsul@ventanamicro.com

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arch/riscv/include/asm/spl.h | 1 + arch/riscv/lib/Makefile | 2 ++ arch/riscv/lib/interrupts.c | 11 +++++++++++ arch/riscv/lib/semihosting.c | 24 ++++++++++++++++++++++++ lib/Kconfig | 6 +++--- 5 files changed, 41 insertions(+), 3 deletions(-) create mode 100644 arch/riscv/lib/semihosting.c

Reviewed-by: Leo Yu-Chi Liang ycliang@andestech.com