Enable ELBC from Kconfig.
Signed-off-by: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com --- Changes for v5: Added first time in the patch set Changes for v6: Sending as it is
arch/powerpc/cpu/mpc85xx/Kconfig | 26 ++++++++++++++++++++++++++ include/configs/MPC8313ERDB.h | 1 - include/configs/MPC8315ERDB.h | 1 - include/configs/MPC837XEMDS.h | 1 - include/configs/MPC837XERDB.h | 1 - include/configs/MPC8536DS.h | 1 - include/configs/MPC8569MDS.h | 2 -- include/configs/MPC8572DS.h | 1 - include/configs/P1022DS.h | 1 - include/configs/P1023RDB.h | 1 - include/configs/P2041RDB.h | 1 - include/configs/UCP1020.h | 1 - include/configs/controlcenterd.h | 1 - include/configs/corenet_ds.h | 1 - include/configs/cyrus.h | 1 - include/configs/ids8313.h | 2 -- include/configs/km/kmp204x-common.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - include/configs/p1_twr.h | 1 - include/configs/ve8313.h | 1 - include/configs/xpedite537x.h | 1 - include/configs/xpedite550x.h | 1 - 22 files changed, 26 insertions(+), 23 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 8c6503d..765d328 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -429,11 +429,13 @@ config ARCH_MPC8536 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_ELBC
config ARCH_MPC8540 bool select FSL_LAW select SYS_FSL_HAS_DDR1 + select FSL_ELBC
config ARCH_MPC8541 bool @@ -442,6 +444,7 @@ config ARCH_MPC8541 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 + select FSL_ELBC
config ARCH_MPC8544 bool @@ -452,6 +455,7 @@ config ARCH_MPC8544 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_ELBC
config ARCH_MPC8548 bool @@ -467,6 +471,7 @@ config ARCH_MPC8548 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_ELBC
config ARCH_MPC8555 bool @@ -475,11 +480,13 @@ config ARCH_MPC8555 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 + select FSL_ELBC
config ARCH_MPC8560 bool select FSL_LAW select SYS_FSL_HAS_DDR1 + select FSL_ELBC
config ARCH_MPC8568 bool @@ -488,6 +495,7 @@ config ARCH_MPC8568 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 + select FSL_ELBC
config ARCH_MPC8569 bool @@ -498,6 +506,7 @@ config ARCH_MPC8569 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 + select FSL_ELBC
config ARCH_MPC8572 bool @@ -512,6 +521,7 @@ config ARCH_MPC8572 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_ELBC
config ARCH_P1010 bool @@ -546,6 +556,7 @@ config ARCH_P1011 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_ELBC
config ARCH_P1020 bool @@ -559,6 +570,7 @@ config ARCH_P1020 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_ELBC
config ARCH_P1021 bool @@ -572,6 +584,7 @@ config ARCH_P1021 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_ELBC
config ARCH_P1022 bool @@ -587,6 +600,7 @@ config ARCH_P1022 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_ELBC
config ARCH_P1023 bool @@ -598,6 +612,7 @@ config ARCH_P1023 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select FSL_ELBC
config ARCH_P1024 bool @@ -611,6 +626,7 @@ config ARCH_P1024 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_ELBC
config ARCH_P1025 bool @@ -624,6 +640,7 @@ config ARCH_P1025 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_ELBC
config ARCH_P2020 bool @@ -638,6 +655,7 @@ config ARCH_P2020 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB + select FSL_ELBC
config ARCH_P2041 bool @@ -659,6 +677,7 @@ config ARCH_P2041 select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select FSL_ELBC
config ARCH_P3041 bool @@ -682,6 +701,7 @@ config ARCH_P3041 select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select FSL_ELBC
config ARCH_P4080 bool @@ -716,6 +736,7 @@ config ARCH_P4080 select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 + select FSL_ELBC
config ARCH_P5020 bool @@ -736,6 +757,7 @@ config ARCH_P5020 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_ELBC
config ARCH_P5040 bool @@ -756,6 +778,7 @@ config ARCH_P5040 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 + select FSL_ELBC
config ARCH_QEMU_E500 bool @@ -1241,6 +1264,9 @@ config SYS_PPC_E500_USE_DEBUG_TLB config FSL_IFC bool
+config FSL_ELBC + bool + config SYS_PPC_E500_DEBUG_TLB int "Temporary TLB entry for external debugger" depends on SYS_PPC_E500_USE_DEBUG_TLB diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 4b0b352..3cf9404 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -55,7 +55,6 @@ #endif
#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_FSL_ELBC 1
#define CONFIG_MISC_INIT_R
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index bd25c0b..e3e47e2 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -185,7 +185,6 @@ #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00040000 -#define CONFIG_FSL_ELBC 1
/* * FLASH on the Local Bus diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index f86b008..64e043c 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -216,7 +216,6 @@ #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 #define CONFIG_SYS_LBC_LBCR 0x00000000 -#define CONFIG_FSL_ELBC 1
/* * FLASH on the Local Bus diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index d843bd1..9b71e9f 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -240,7 +240,6 @@ #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 #define CONFIG_SYS_LBC_LBCR 0x00000000 -#define CONFIG_FSL_ELBC 1
/* * FLASH on the Local Bus diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index ce33405..836db05 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -37,7 +37,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif
-#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 3e00f69..6e2642d 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ - #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 5ca01e8..d7b1366 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -28,7 +28,6 @@ /* High Level Configuration Options */ #define CONFIG_MP 1 /* support multiple processors */
-#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 505b417..e4806cc 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -96,7 +96,6 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif
-#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index d8ff10e..1aa8fcc 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -25,7 +25,6 @@ /* High Level Configuration Options */ #define CONFIG_MP /* support multiple processors */
-#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 3cd5c3c..fd3e116 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -41,7 +41,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index f32fb4d..2ea38c7 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -14,7 +14,6 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#define CONFIG_FSL_ELBC #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 1736097..da05aa0 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -137,7 +137,6 @@ /* * Local Bus Definitions */ -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_SYS_ELBC_BASE 0xe0000000 #ifdef CONFIG_PHYS_64BIT diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index c9c00c5..1f3b735 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -59,7 +59,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 14e207e..f399858 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -49,7 +49,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 112e885..951eb3d 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -19,8 +19,6 @@ #define CONFIG_MPC8313 #define CONFIG_IDS8313
-#define CONFIG_FSL_ELBC - #define CONFIG_MISC_INIT_R
#define CONFIG_BOOT_RETRY_TIME 900 diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index b4cdb67..d7f968f 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -35,7 +35,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index f91a762..9555aa2 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -260,7 +260,6 @@
#define CONFIG_MP
-#define CONFIG_FSL_ELBC #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 63825b0..d50bc15 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -40,7 +40,6 @@
#define CONFIG_MP
-#define CONFIG_FSL_ELBC #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index e293f12..a0a2453 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -26,7 +26,6 @@ #endif
#define CONFIG_PCI_INDIRECT_BRIDGE 1 -#define CONFIG_FSL_ELBC 1
#define CONFIG_BOARD_EARLY_INIT_F 1
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 5d78560..2f133d2 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -29,7 +29,6 @@ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#define CONFIG_FSL_ELBC 1
/* * Multicore config diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 35e6350..76e3db1 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -30,7 +30,6 @@ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#define CONFIG_FSL_ELBC 1
/* * Multicore config