The XEA board now has several HW revisions for both SoM and base boards. This patch provides support for reading those revision ID values in SPL (u-boot.sb) and then pass this information to u-boot proper, as the maximal SPL size (~55KiB) is not allowing for having FIT support in it.
It was necessary to handle reading GPIOs values solely in u-boot proper as one configuration (i.e. 'single binary' - imx28_xea_sb_defconfig) is not using SPL framework.
Signed-off-by: Lukasz Majewski lukma@denx.de ---
board/liebherr/xea/spl_xea.c | 11 +++++++++++ board/liebherr/xea/xea.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+)
diff --git a/board/liebherr/xea/spl_xea.c b/board/liebherr/xea/spl_xea.c index 551ed6fbae..71194db235 100644 --- a/board/liebherr/xea/spl_xea.c +++ b/board/liebherr/xea/spl_xea.c @@ -230,6 +230,17 @@ const iomux_cfg_t iomux_setup[] = { /* TIVA boot control */ MX28_PAD_GPMI_RDY3__GPIO_0_23 | MUX_CONFIG_BOOT, /* TIVA0 */ MX28_PAD_GPMI_WRN__GPIO_0_25 | MUX_CONFIG_BOOT, /* TIVA1 */ + + /* HW revision ID Base Board */ + MX28_PAD_LCD_D12__GPIO_1_12, + MX28_PAD_LCD_D13__GPIO_1_13, + MX28_PAD_LCD_D14__GPIO_1_14, + + /* HW revision ID (SoM) */ + MX28_PAD_LCD_D15__GPIO_1_15, + MX28_PAD_LCD_D16__GPIO_1_16, + MX28_PAD_LCD_D17__GPIO_1_17, + MX28_PAD_LCD_D18__GPIO_1_18, };
u32 mxs_dram_vals[] = { diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c index c8ac526cb4..d9cf27c81b 100644 --- a/board/liebherr/xea/xea.c +++ b/board/liebherr/xea/xea.c @@ -48,6 +48,35 @@ DECLARE_GLOBAL_DATA_PTR; * Functions */
+/* + * Reading the HW ID number for XEA SoM module + * + * GPIOs from Port 1 (GPIO1_15, GPIO1_16, GPIO1_17 and GPIO1_18) + * are used to store HW revision information. + * Reading of GPIOs values is performed before the Device Model is + * bring up as the proper DTB needs to be chosen first. + * + * Moreover, this approach is required as "single binary" configuration + * of U-Boot (imx28_xea_sb_defconfig) is NOT using SPL framework, so + * only minimal subset of functionality is provided when ID is read. + * + * Hence, the direct registers' access. + */ +#define XEA_SOM_HW_ID_GPIO_PORT (MXS_PINCTRL_BASE + (0x0900 + ((1) * 0x10))) +#define XEA_SOM_REV_MASK GENMASK(18, 15) +#define XEA_SOM_REV_SHIFT 15 + +static inline u8 get_som_rev(void) +{ + struct mxs_register_32 *reg = + (struct mxs_register_32 *)XEA_SOM_HW_ID_GPIO_PORT; + + u32 tmp = ~readl(®->reg); + u8 id = (tmp & XEA_SOM_REV_MASK) >> XEA_SOM_REV_SHIFT; + + return id; +} + static void init_clocks(void) { /* IO0 clock at 480MHz */